Received-signal absolute phasing apparatus of receiver

ABSTRACT

When reception of a multiplexed wave to be PSK-modulated of BPSK, QPSK, and 8PSK is started, a selector ( 16 A) of a demodulating circuit ( 1 A) reads high-order three bits Δφ( 3 ) of phase error data corresponding to I and Q symbol streams out of one phase error table ( 15 - 1 ) for BPSK among phase error tables provided for each modulation system and each phase rotation angle. A received-signal-phase rotation angle detecting circuit ( 8 A) detects phase rotation angles of portions corresponding to bits ( 1 ) and ( 0 ) of a frame-synchronizing signal of a received symbol stream from the Δφ( 3 ) and the MSB of I symbol stream and outputs the phase rotation angles to a remapper ( 7 ) to make the remapper perform absolute phasing. The selector ( 16 A) reads phase error data corresponding to a received symbol stream out of a phase error table corresponding to a modulation system and a phase rotation angle identified by a transmission-configuration identifying circuit ( 9 ), outputs the phase error data to a D/A converter ( 17 ), corrects a phase of a reference carrier wave for orthogonal detection, and makes a received-signal point become a constant phase for a transmitted-signal point.

TECHNICAL FIELD

The present invention relates to an received-signal absolute phasingapparatus of receiver, particularly to a received-signal absolutephasing apparatus of receiver, which makes the following coincide withthe transmission side: signal point arrangements of received I and Qbase-band signals of two series obtained by receiving and demodulating:a signal to be PSK-modulated in which at least an 8PSK-modulated digitalsignal among 8PSK-modulated digital signal, QPSK-modulated digitalsignal, and BPSK-modulated digital signal are time-multiplexed with aBPSK-modulated frame synchronizing signal, by a hierarchicaltransmission system; or a signal to be PSK-modulated in which at least8PSK-modulated digital signal and QPSK-modulated digital signal among8PSK-modulated digital signal, QPSK-modulated digital signal, andBPSK-modulated digital signal are time-multiplexed with a BPSK-modulatedframe synchronizing signal, by the system.

BACKGROUND ART

Practical use of digital satellite TV broadcasting is advanced whichuses a plurality of modulation systems different from each other inrequired C/N such as a hierarchical transmission system for repeatedlytransmitting a wave to be 8PSK-modulated, a wave to be QPSK-modulated,and a wave to be BPSK-modulated by time-multiplexing the waves.

FIG. 11A is an illustration showing a frame configuration of ahierarchical transmission system. One frame is configured by a framesynchronizing signal pattern comprising 32 BPSK-modulated symbols (among32 symbols, 20 latter-half symbols are actually used as a framesynchronizing signal), a TMCC (Transmission and MultiplexingConfiguration Control) pattern for identifying a transmissionmultiplexing configuration comprising 128 BPSK-modulated symbols, asuper-frame-identifying signal pattern comprising 32 symbols (among 32symbols, 20 latter-half symbols are actually used as asuper-frame-identifying signal), main signal of 2038PSK(trellis-CODEC-8PSK)-modulated symbols, burst symbol signal (BS) of4 symbols obtained by BPSK-modulating a pseudo random-noise (PN) signal,main signal of 203 8PSK(trellis-CODEC-8PSK)-modulated symbols, burstsymbol signal (BS) of 4 symbols obtained by BPSK-modulating a pseudorandom-noise (PN) signal, . . . , main signal of 203 QPSK-modulatedsymbols, burst symbol signal (BS) of 4 symbols obtained byBPSK-modulating a pseudo random-noise (PN) signal, main signal of 203QPSK-modulated symbols, and burst symbol signal (BS) of 4 BPSK-modulatedsymbols in order.

In case of a receiver for receiving digital waves to be modulated (wavesto be PSK-modulated) according to the hierarchical transmission system,an intermediate-frequency signal of a received signal received by areceiving circuit is demodulated by a demodulating circuit and I and Qbase-band signals of two series showing instantaneous values of I axisand Q axis orthogonal to each other every symbol (hereafter, I and Qbase-band signals are also referred to as I and Q symbol stream datavalues) are obtained. By acquiring a frame synchronizing signal from thedemodulated I an Q base-band signals, obtaining a presentreceived-signal-phase rotation angle from the signal point arrangementof the acquired frame synchronizing signal, and antiphase-rotating thedemodulated I and Q base-band signals in accordance with the obtainedreceived-signal-phase rotation angle, absolute phase generation foradjusting the I and Q base-band signals to a transmission-signal phaseangle is performed by an absolute-angle-generating circuit.

As shown in FIG. 12, an absolute-phase generating circuit of a receiverfor receiving waves to be PSK-modulated according to a conventionalhierarchical transmission system is configured by a frame syncdetecting/regenerating circuit 2 serving as frame sync acquiring meansprovided for the output side of a demodulating circuit 1 to acquire aframe synchronizing signal, a remapper 7 serving as antiphase rotatingmeans comprising a ROM, and received-signal-phase rotation angledetecting circuit 8 serving as received-signal-phase rotation angledetecting means. Symbol 9 denotes a transmission-configurationidentifying circuit for identifying a transmission multiplexingconfiguration shown in FIG. 11A, which outputs a 2-bit-modulating-systemidentifying signal DM.

The demodulating circuit 1 obtains I and Q base-band signals byquadrature-detecting an intermediate frequency signal IF. In thedemodulating circuit 1, symbol 10 denotes a carrier-wave regeneratingcircuit for regenerating two reference carrier waves f_(c1) (=cos ωt)and f_(c2) (=sin ωt) whose frequencies and phases synchronize with areceived carrier wave and which is orthogonal to each other becausetheir phase are shifted by 90° from each other, 60 and 61 denotemultipliers for multiplying the intermediate frequency signal IF byf_(c1) and f_(c2), 62 and 63 denote A/D converters for A/D-convertingoutputs of the multipliers 60 and 61 at a sampling rate two times largerthan a symbol rate, 64 and 65 denote digital filters for performing bandrestriction to outputs of the A/D converters 62 and 63 through digitalsignal processing, and 66 and 67 denote thinning circuits for thinningoutputs of the digital filters 64 and 65 at a ½ sampling rate andoutputting I and Q base-band signals (I and Q symbol stream data values)of two series showing instantaneous values of I-axis and Q-axis everysymbol. The thinning circuits 66 and 67 transmit I and Q base-bandsignals I(8) and Q(8) (a numeral in parentheses shows the number ofquantization bits and is hereafter also simply referred to as I and Q byomitting the number of quantization bits) having 8 quantization bits(two's complement system).

Mapping for each modulation system at the transmission side will bedescribed below by referring to FIGS. 13A-13C. FIG.13A shows signalpoint arrangements on an I-Q phase plane (also referred to as I-Q vectorplane or I-Q signal space diagram) using 8PSK for a modulation system.The 8PSK modulation system makes it possible to transmit a 3-bit digitalsignal (abc) by one symbol. Combination of bits configuring one symbolincludes eight ways such as (000), (001), (010), (011), (100), (101),(110), and (111). These 3-bit digital signals are converted into signalpoint arrangements “0” to “7” on the transmission-side I-Q phase planein FIG. 13A and this conversion is referred to as 8PSK mapping.

In case of the example shown in FIG. 13A, the bit string (000) isconverted into a signal point arrangement “0”, the bit string (001) intoa signal point arrangement “1”, the bit string (011) into a signal pointarrangement “2”, the bit string (010) into a signal point arrangement“3”, the bit string (100) into a signal point arrangement “4”, the bitstring (101) into a signal point arrangement “5”, the bit string (111)into a signal point arrangement “6”, and the bit string (110) into asignal point arrangement “7”.

FIG. 13B shows signal point arrangements on an I-Q phase plane at thetime of using QPSK for a modulation system. The QPSK modulation systemmakes it possible to transmit a 2-bit digital signal (de) by one symbol.Combination of bits configuring the symbol includes four ways such as(00), (01), (10), and (11). In case of the example in FIG. 13B, the bitstring (00) is converted into a signal point arrangement “1”, the bitstring (01) into a signal point arrangement “3”, the bit string (11)into a signal point arrangement “5”, and the bit string (10) into asignal point arrangement “7”.

FIG. 13C shows signal point arrangements at the time of using BPSK for amodulation system. The BPSK modulation system transmits a 1-bit signal(f) by one symbol. In case of the digital signal (f), bit (0) isconverted into a signal point arrangement “0” and bit (1) is convertedinto a signal point arrangement “4”. Relations between signal pointarrangements and arrangement numbers of modulation systems are the sameeach other on the basis of 8BPSK.

I axis and Q axis of QPSK and BPSK in the hierarchical transmissionsystem coincide with I axis and Q axis of 8PSK.

When the phase of a received carrier wave coincides with the phase ofthe reference carrier wave f_(c1) or f_(c2) regenerated by thecarrier-wave regenerating circuit 10, the phase of the received-signalpoint on the I-Q phase plane according to I and Q base-band signals I(8)and Q(8) at the reception side at the time of receiving digital signalscorresponding to signal point arrangements “0” to “7” on the I-Q phaseplane at the transmission side coincide with those of the transmissionside. Therefore, by directly using the relations between signal pointarrangements and digital signals at the transmission side (refer toFIGS. 13A-13C), it is possible to correctly identify a digital signalreceived from a signal point arrangement of a received-signal point.

In fact, however, the reference carrier wave f_(c1) or f_(c2) can takevarious phase states for a received carrier wave. Therefore, areceived-signal point at the reception side is located at a phaseposition rotated by a certain angle θ from the transmission side.Moreover, when a phase of a received carrier wave fluctuates, θ alsofluctuates. When the phase of the received signal point rotates from thetransmission side at random, it becomes impossible to identify areceived digital signal. For example, when θ is equal to π/8, thereceived-signal point of the digital signal (000) of the signal pointarrangement “0” in the 8PSK modulation system at the transmission sideis located between the signal point arrangements “0” and “1” at thereception side. Therefore, at the time of assuming that the digitalsignal (000) is received at the signal point arrangement “0”, it isjudged that the signal (000) is correctly received. However, at the timeof assuming that the digital signal (000) is received at the signalpoint arrangement “1”, it is erroneously judged that the digital signal(001) is received. Therefore, for a received-signal point to keep acertain rotation angle from the transmission side, the carrier-waveregenerating circuit 10 corrects phases of the reference carrier wavesf_(c1) and f_(c2) so that a digital signal can be correctly identified.

Specifically, by making a VCO (voltage control oscillator) 11 of thecarrier-wave regenerating circuit 10 oscillate at a transmission carrierwave frequency, the reference carrier wave f_(c1) is generated andmoreover, the reference carrier wave f_(c2) is generated by advancing aphase of an oscillation signal of the VCO 11 by 90° by a 90° phaseshifter 12. Then, by changing control voltages of the VCO 11, phases ofthe reference carrier wave f_(c1) or f_(c2) can be changed.

The carrier-wave regenerating circuit 10 is provided with phase errortables 13, 14-1 and 14-2, and 15-1 to 15-4 respectively configured by aROM and formed by tabulating relations between various data sets of theI and Q base-band signals I(8) and Q(8) and carrier-wave phase errordata having 8 quantization bits (two's complement system) (hereafteralso simply referred to as phase error data) Δφ(8) (refer to FIG. 14) bymodulation systems of 8PSK, QPSK and BPSK. The I and Q base-band signalsI(8) and Q(8) are input to the phase error tables 13, 14-1 and 14-2, and15-1 to 15-4 in parallel. A phase error table selectively enabled by aselector to be described later outputs the phase error data Δφ(8)corresponding to the I and Q base-band signals I(8) and Q(8) input fromthe demodulating circuit 1.

The phase error table 13 is used for 8PSK, in which the relation betweena phase angle φ (refer to FIG. 15) on the I-Q phase plane of thereceived-signal point shown by the I and Q base-band signals I(8) andQ(8) input from the demodulating circuit 1 and the phase error dataΔφ(8) is configured as shown in FIG. 17. A selector 16 enables only thephase error table 13 (makes only the phase error table 13 active) whilethe demodulating circuit 1 demodulates digital waves to be modulated inaccordance with the BPSK modulation system (specified by amodulation-system identifying signal DM supplied from atransmission-configuration identifying circuit 9 to be described later)in accordance with a clock CLK_(SYB) (refer to FIG. 11B) having a symbolrate synchronous with outputs of the I and Q base-band signals I(8) andQ(8) supplied from the demodulating circuit 1 and reads the phase errordata Δφ(8) corresponding to the set data of the I(8) and Q(8) wheneverthe demodulating circuit 1 outputs the I and Q base-band signals I(8)and Q(8) for one symbol. The phase error data Δφ(8) is converted into aphase error voltage by a D/A converter 17 and thereafter, low-frequencycomponents are fetched from the phase error voltage by an LPF 18 and thevoltage is applied to the VCO 11 as a control voltage. When the phaseerror data Δφ(8) is equal to 0, outputs of the LPF 18 are not changed orphases of the reference carrier wave f_(c1) or f_(c2) are not changed.However, when the phase error data Δφ(8) is positive, outputs of the LPF18 increase and phases of the reference carrier waves f_(c1) and f_(c2)are delayed. However, when the phase error data Δφ(8) is negative,outputs of the LPF 18 decrease and phases of the reference carrier wavesf_(c1) and f_(c2) are advanced.

In the phase error table 13, the difference between φ and the phase ofthe nearest one of the signal point arrangements “0” to “7” serves asthe phase error data Δφ(8). Therefore, positions of digital signals ofsignal point arrangements of 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4, and7π/4 according to the 8PSK modulation system at the transmission sideare respectively corrected to a position rotated by Θ=m×π/4 (m=one ofintegers 0 to 7: refer to FIG. 16) on the I-Q phase plane at thereception side. Symbol Θ denotes a received-signal phase rotation angle.Thereby, because received-signal points according to the 8PSK modulationsystem are brought to positions of phases 0, π/4, 2π/4, 3π/4, 4π/4,5π/4, 6π/4, and 7π/4, it is possible to assign the signal pointarrangements “0” to “7” on the I-Q phase plane at the reception side tothe same phases as that of the transmission side (However, the relationbetween a signal point arrangement and a digital signal is changed inaccordance with Θ.). By detecting Θ and antiphase-rotating it by −Θ, itis possible to make the relation between a signal point arrangement anda digital signal same as that of the transmission side (absolute phasegeneration) and easily identify a received digital signal.

The phase error tables 14-1 and 14-2 are used for QPSK and the relationbetween phase angle φ and phase error data Δφ(8) on the I-Q phase planeof the received-signal point shown by the I and Q base-band signals I(8)and Q(8) is configured as shown in FIGS. 18 and 19. Under normalreception, the selector 16 enables only the phase error table 14-1 whenthe received-signal phase rotation angle Θ is equal to 0, 2π/4, 4π/4, or6π/4 while the demodulating circuit 1 demodulates digital waves to bemodulated according to the OPSK modulation system in accordance with aclock CLK_(SYB) having a symbol rate and reads the phase error dataΔφ(8) corresponding to the set data for I and Q base-band signals I(8)and Q(8) for one symbol out of the phase error table 14-1 whenever thedemodulating circuit 1 outputs the I and Q base-band signals I(8) andQ(8).

In the phase error table 14-1, the difference between φ and the phase ofthe nearest one of the signal point arrangements “1”, “3”, “5”, and “7”serves as the phase error data Δφ. Therefore, positions of digitalsignals of the signal point arrangements “1”, “3”, “5”, and “7” of thephases π/4, 3π/4, 5π/4, and 7π/4 according to the QPSK modulation systemat the transmission side are respectively corrected to a positionrotated by Θ on the I-Q phase plane at the reception side. When Θ isequal to 0, 2π/4, 4π/4, or 6π/4, a received-signal point according tothe QPSK modulation system is brought to a position of π/4, 3π/4, 5π/4,or 7π/4. By detecting Θ and antiphase-rotating it by −Θ, it is possibleto make the relation between a signal point arrangement and a digitalsignal same as that of the transmission side (absolute phase generation)and easily identify a received digital signal.

Moreover, the selector 16 enables only the phase error table 14-2 when Θis equal to π/4, 3π/4, 5π/4, or 7π/4 while the demodulating circuit 10demodulates digital waves to be modulated according to the QPSKmodulation system and reads the phase error data Δφ(8) corresponding tothe set data of the I and Q base-band signals I(8) and Q(8) for onesymbol out of the phase error table 14-2 whenever the demodulatingcircuit 1 outputs the I and Q base-band signals I(8) and Q(8).

In the phase error table 14-2, the difference between f and the phase ofthe nearest one of the signal point arrangements “0”, “2”, “4”, and “6”serves as the phase error data Δφ. Therefore, positions of digitalsignals of the signal point arrangements “1”, “3”, “5”, and “7” of thephases π/4, 3π/4, 5π/4, and 7π/4 according to the QPSK modulation systemat the transmission side are respectively corrected to a positionrotated by the above Θ. When Θ is equal to π/4, 3π/4, 5π/4, or 7π/4, areceived-signal point according to the QPSK modulation system is broughtto the position of the phase Θ, 2π/4, 4π/4, or 6π/4. By detecting Θ andantiphase-rotating it by −Θ, it is possible to obtain the same phase asthat of the transmission side (absolute phase generation), make therelation between a signal point arrangement and a digital signal same asthat of the transmission side, and easily identify a received digitalsignal.

The phase error tables 15-1 to 15-4 are used for BPSK and the relationbetween the phase angle φ and the phase error data Δφ(8) on the I-Qphase plane of the received-signal point shown by the I and Q base-bandsignals I(8) and Q(8) is configured as shown in FIGS. 20 to 23. Selector16 enables only the phase error table 14-1 when the received-signalphase rotation angle Θ is equal to 0 or 4π/4 while the demodulatingcircuit 1 demodulates digital waves to be modulated according to theBPSK modulation system synchronously with a clock CLK_(SYB) having asymbol rate and reads the phase error data Δφ(8) corresponding to theset data for the I and Q base-band signals I(8) and Q(8) for one symbolout of the phase error table 15-1 whenever the demodulating circuit 1outputs the base band signals I(8) and Q(8).

In the phase error table 15-1, the difference between φ and the phase ofthe nearest one of the signal point arrangements “0” and “4” serves asthe phase error data Δφ. Therefore, positions of digital signals of thesignal point arrangements “0” and “4” of the phases 0 and 4π/4 accordingto the BPSK modulation system at the transmission side are respectivelycorrected to a position rotated by the above Θ on the I-Q phase plane atthe reception side. When Θ is equal to 0 or 4π/4, a received-signalpoint according to the BPSK modulation system is brought to the positionof the phase 0 or 4π/4.

Moreover, the selector 16 enables only the phase error table 15-2 when Θis equal to π/4 or 5π/4 while digital waves to be modulated aredemodulated in accordance with the BPSK modulation system and reads thephase error data Δφ(8) corresponding to the set data for the I and Qbase-band signals I(8) and Q(8) for one symbol out of the phase errortable 15-2 whenever the demodulating circuit 1 outputs the I and Qbase-band signals I(8) and Q(8).

In the phase error table 15-2, the difference between φ and the phase ofthe nearest one of the signal point arrangements “1” and “5” serves asthe phase error data Δφ. Therefore, positions of digital signals of thesignal point arrangements “0” and “4” of the phases 0 and 4π/4 accordingto the BPSK modulation system at the transmission side are respectivelycorrected to a position rotated by the above Θ on the I-Q phase plane atthe reception side. When Θ is equal to π/4 or 5π/4, a received-signalpoint according to the BPSK modulation system is brought to the positionof the phase π/4 or 5π/4.

Moreover, the selector 16 enables only the phase error table 15-3 when Θis equal to 2π/4 or 6π/4 while demodulating digital waves to bemodulated in accordance with the BPSK modulation system and reads thephase error data Δφ(8) corresponding to the set data for the I and Qbase-band signals I(8) and Q(8) for one symbol from the phase errortable 15-3 whenever the demodulating circuit 1 outputs the I(8) andQ(8).

In the phase error table 15-3, the difference between φ and the phase ofthe nearest one of the signal point arrangements “2” and “6” serves asthe phase error data Δφ. Therefore, positions of digital signals of thesignal point arrangements “0” and “4” of the phases 0 and 4π/4 accordingto the BPSK modulation system at the transmission side are respectivelycorrected to a position rotated by the above Θ on the I-Q phase plane atthe reception side. When Θ is equal to 2π/4 or 6π/4, a received-signalpoint according to the BPSK modulation system is brought to the positionof the phase 2π/4 or 6π/4.

Moreover, the selector 16 enables only the phase error table 15-4 when Θis equal to 3π/4 or 7π/4 while demodulating digital waves to bemodulated according to the BPSK modulation system and reads the phaseerror data Δφ(8) corresponding to the set data for the I and Q base-bandsignals I(8) and Q(8) for one symbol out of the phase error table 15-4whenever the demodulating circuit 1 outputs the I(8) and Q(8).

In the phase error table 15-4, the difference between φ and the phase ofthe nearest one of the signal point arrangements “3” and “7” serves asthe phase error data Δφ. Therefore, positions of digital signals of thesignal point arrangements “0” and “4” of the phases 0 and 4π/4 accordingto the BPSK modulation system at the transmission side are respectivelycorrected to a position rotated by the above E) on the I-Q phase planeat the reception side. When Θ is equal to 3π/4 or 7π/4, areceived-signal point according to the BPSK modulation system is broughtto the position of the phase 3π/4 or 7π/4. Also in the case of BPSKmodulation, by detecting Θ and antiphase-rotating it by −Θ, it ispossible to obtain the same phase as that of the transmission side(absolute phase generation), make the relation between a signal pointarrangement and a digital signal same as that of the transmission side,and easily identify a received digital signal.

As shown in FIG. 24, the frame sync detecting/regenerating circuit 2 isconfigured by a BPSK demapper 3, sync detecting circuits 40 to 47, aframe synchronizing circuit 5, an OR gate circuit 53, and aframe-synchronizing-signal generator 6. The received-signal-phaserotation angle detecting circuit 8 is configured by delay circuits 81and 82, a 0°/180° phase rotating circuit 83, averaging circuits 85 and86, and a received-phase judging circuit 87.

The I and Q base-band signals I(8) and Q(8) output from the demodulatingcircuit 1 are input to a BPSK demapper section 3 of the frame syncdetecting/regenerating circuit 2 in order to acquire, for example, aBPSK-modulated frame synchronizing signal and a BPSK-demapped bit streamB0 is output. The BPSK demapper section 3 is configured by, for example,a ROM.

Then, a frame-synchronizing signal will be described below. In case ofthe hierarchical transmission system, a frame synchronizing signal isBPS-modulated at a required lowest C/N and transmitted. A framesynchronizing signal configured by 20 bits has a bit stream of (S0S1 . .. S18S19)=(11101100110100101000) which are transmitted in order startingwith S0. A bit stream of a frame-synchronizing signal is also referredto as “SYNCPAT”. The bit stream is converted into the signal pointarrangement “0” or “4” through the BPSK mapping shown in FIG. 13C at thetransmission side and a converted symbol stream is transmitted.

To acquire BPSK-modulated and transmitted 20 bits, that is, a framesynchronizing signal of 20 symbols, it is necessary to convert areceived symbol into a bit through the BPSK demapping shown in FIG. 25Ainversely to the mapping converted at the transmission side. Therefore,as shown in FIG. 25A, a demodulated signal is judged as (0) when thesignal is received in the hatched area on the I-Q phase plane at thereception side and the signal is judged as (1) when it is received inthe not-hatched area. That is, an output is classified into (0) or (1)depending on the fact that the output is received in which area of twojudgment areas divided by a BPSK judging borderline shown by a bold linein FIG. 25A and thereby, it is assumed that BPSK demapping is performed.

The I and Q base-band signals I(8) and Q(8) are input to the BPSKdemapper section 3 in order to undergo the BPSK demapping and a bitstream B0 BPSK-demapped in the BPSK demapper section 3 is output. Inthis specification, a demapper denotes a circuit for performingdemapping. The bit stream B0 is input to the sync detecting circuit 40in which a bit stream of a frame-synchronizing signal is acquired fromthe bit stream B0.

Then, the sync detecting circuit 40 will be described below by referringto FIG. 26. The sync detecting circuit 40 has 20 D-flip-flops (hereafterreferred to as D-F/Fs) D19 to D0 connected in series and a 20-stageshift register is configured by these D-F/Fs D19 to D0. The bit streamB0 is input to the D-F/F D19 and successively shifted up until D-F/F D0and at the same time, logic inversion is applied to predetermined bitsof outputs of the D-F/F D19 to D-F/F D0 and then, the outputs are inputto an AND gate 51. In the AND gate 51, when output states (D0D1 . . .D18D19) of the D-F/F D19 to D0 are set to (11101100110100101000), anoutput SYNA0 of the AND gate 51 becomes a high potential. That is, whena SYNCPAT is acquired, the SYNA0 becomes a high potential.

The output SYNA0 of the sync detecting circuit 40 is input to the framesynchronizing circuit 5 through the OR gate circuit 53. In the framesynchronizing circuit 5, it is judged that frame sync is effectuatedwhen it is confirmed that an output SYA of the OR gate circuit 53repeatedly becomes a high potential every certain frame cycle and aframe synchronizing pulse is output every frame cycle.

Usually, in case of a hierarchical transmission system to which aplurality of modulation systems having necessary C/Ns different fromeach other are time-multiplexed and repeatedly transmitted every frame,header data values showing their multiple configurations are multiplexed(TMCC pattern in FIG. 11A). The transmission-configuration identifyingcircuit 9 extracts TMCC showing a multiple configuration from a bitstream after BPSK demapper input from the frame synchronizing circuit 5after it is judged by the frame sync detecting/regenerating circuit 2that frame sync is effectuated, decodes the TMCC, and outputs amodulation-system identifying signal DM showing by which modulationsystem the present I and Q base-band signals I and Q are generated tothe selector 16 (refer to FIG. 11B). Moreover, the received-signal phaserotation angle detecting circuit 8 detects a received-signal phaserotation angle Θ in accordance with a regenerated-frame synchronizingsignal output from the frame-synchronizing-signal generator 6 after itis judged by the frame sync detecting/regenerating circuit 2 that framesync is effectuated and outputs a 3-bit received-signal phase rotationangle signal AR(3) to the remapper 7 and the selector 16 of the carrierwave regenerating circuit 10.

The selector 16 of the carrier wave regenerating circuit 10 reads thephase error data Δφ(8) from a phase error table corresponding to amodulation system and the received-signal phase rotation angle Θ afterthe modulation system identifying signal DM is input from thetransmission configuration identifying circuit 9 and moreover, thereceived-signal phase rotation angle signal AR(3) is input from thereceived-signal phase rotation angle detecting circuit 8 and outputs thephase error data Δφ(8) to the D/A converter 17. Until then, however, theselector 16 reads the phase error data Δφ(8) out of the phase errortable 13 for 8PSK.

Thus, until the transmission configuration identifying circuit 9identifies a multiple configuration and the received-signal phaserotation angle detecting circuit 8 detects the received-signal phaserotation angle Θ, the demodulating circuit 1 always operates as an 8PSKdemodulating circuit. Therefore, a received-signal point rotates byΘ=m×π/4 (m is one of integers 0 to 7) from the transmission sidedepending on a phase state of the reference carrier wave f_(c1) orf_(c2) regenerated by the carrier wave regenerating circuit 10 of thedemodulating circuit 1.

That is, as shown in FIG. 13C, a received-signal point of a symbolstream of a frame synchronizing signal BPSK-mapped to the signal pointarrangement “0” for the bit (0) or BPSK-mapped to the signal pointarrangement “4” for the bit (1) at the transmission side appears on oneof the following cases depending on a phase state of the referencecarrier wave f_(c1) or f_(c2): the signal point arrangement “0” or “4”where Θ equals 0 similarly to the case of the transmission side, signalpoint arrangement “1” or “5” rotated by Θ=π/4 phases, signal pointarrangement “2” or “6” rotated by Θ=2π/4 phases, the signal pointarrangement “3” or “7” rotated by Θ=3π/4 phases, signal pointarrangement “4” or “0” rotated by Θ=4π/4 phases, signal pointarrangement “5” or “1” rotated by Θ=5π/4 phases, signal pointarrangement “6” or “2” rotated by Θ=6π/4 phases, and signal pointarrangement “7” or “3” rotated by Θ=7π/4 phases. Thus, a demodulatedframe synchronizing signal has eight phase states. Therefore, even whena frame-synchronizing signal is demodulated in any phase, the signalmust be acquired.

Therefore, the BPSK demapper section 3 is configured by BPSK demappers30 to 37 corresponding to phase rotations of Θ=0 (m=0), Θ=7π/4 (m=1),Θ=2π/4 (m=2), Θ=3π/4 (m=3), Θ=4π/4 (m=4), Θ=5π/4 (m=5), Θ=6π/4 (m=6),and Θ=7π/4 (m=7).

FIG. 25B shows BPSK demapping corresponding to a case in which a symbolstream of a demodulated frame synchronizing signal rotates by Θ=π/4 andthe bit (0) appears on the signal point arrangement “1” and the bit (1)appears on the signal point arrangement “5”. The BPSK judging borderlineshown by the bold line in FIG. 25B rotates by π/4 counterclockwise fromthe BPSK judging borderline of the BPSK demapping shown by the bold linein FIG. 25A at the time of reception at the same phase as that oftransmission side. By using the BPSK demapper (refer to symbol 31 inFIG. 27) for performing the BPSK demapping shown in FIG. 25B, it ispossible to stably acquire a frame synchronizing signal whose phase isrotated by Θ=π/4. A bit stream BPSK-demapped by the BPSK demapper 31serves as an output B1 of the BPSK demapper section 3 in FIG. 24.

Similarly, the BPSK demappers 32 to 37 perform BPSK demapping at BPSKjudging borderlines rotated by 2π/4, 3π/4, . . . , and 7π/4counterclockwise from the BPSK judging borderline for BPSK demappingshown by the bold line in FIG. 25A to stably acquire frame synchronizingsignals phase-rotated by Θ=2π/4, 3π/4, . . . , and 7π/4. Bit streamsBPSK-demapped by the BPSK demappers 32 to 37 serve as outputs B2 to B7of the BPSK demapper section 3 in FIG. 24. The BPSK demapper 30 performsBPSK demapping at the BPSK judging borderline shown by the bold line forBPSK demapping in FIG. 25A to stably acquire a frame synchronizingsignal of Θ=0. A bit stream BPSK-demapped by the BPSK demapper 30 servesas an output B0 of the BPSK demapper section 3 in FIG. 24.

Configurations of sync detecting circuits 41 to 47 are the same as theconfiguration of the sync detecting circuit 40. By using the syncdetecting circuits 40 to 47, a frame synchronizing signal is acquired byone of the sync detecting circuits 40 to 47 independently of phaserotation of a base band signal due to a phase state of the referencecarrier wave f_(c1) or f_(c2) regenerated by the carrier-waveregenerating circuit 10 of the demodulating circuit 1 and ahigh-potential SYNAn (n=integer of 0 to 7) is transmitted from a syncdetecting circuit acquiring the frame synchronizing signal.

The SYNAn output from the sync detecting circuits 40 to 47 is input tothe OR gate circuit 53 and a logical sum SYNA of the SNYAn is outputfrom the OR gate circuit 53. The frame synchronizing circuit 5 judgesthat frame sync is effectuated when it is confirmed that a highpotential of the SYNA is alternately repeatedly input every certainframe interval and outputs a frame synchronizing pulse FSYNC every framecycle. The frame-synchronizing-signal generator 6 generates a bit stream(referred to as regenerated frame-synchronizing signals) same as apattern SYNCPAT of frame-synchronizing signals acquired by the BPSKdemapper 3, synch detecting circuits 40 to 47, and theframe-synchronizing circuit 5 in accordance with a frame-synchronizingpulse FSYNC output from the frame-synchronizing circuit 5.

The above described is a process until a frame-synchronizing signal isacquired from I and Q symbol stream data I(8) and Q(8) output from thedemodulating circuit 1 by the frame-sync detecting/regenerating circuit2 shown in FIG. 24 and a certain time later, a regeneratedframe-synchronizing signal is output from the frame synchronizing-signalgenerator 6.

Then, a transmission-configuration identifying operation by thetransmission-configuration identifying circuit 9 will be describedbelow.

The transmission-configuration identifying circuit 9 receives bitstreams B0 to B7 output by the BPSK demapper 3 of the frame-syncdetecting/regenerating circuit 2, SYNA0 to SYNA7 output by the syncdetecting circuits 40 to 47, and a frame-synchronizing pulse FSYNCoutput by the frame-synchronizing circuit 5. When the circuit 9 receivesthe frame-synchronizing pulse FSYNC, it captures a bit stream Bn of asystem repeatedly kept at a high potential among SYNA0 to SYNA7,extracts the TMCC pattern in FIG. 11A by using a predetermined timingsignal generated in accordance with the frame-synchronizing pulse FSYNC,decodes the pattern, and outputs a modulation-system identifying signalDM showing a modulation system on which the present I and Q base-bandsignals I and Q depend (refer to FIG. 11B).

Then, absolute-phase generation is described which is realized byobtaining the present received-signal-phase rotation angle from a signalpoint arrangement of an acquired frame-synchronizing signal andantiphase-rotating demodulated I and Q base-band signals I(8) and Q(8)in accordance with the obtained received-signal-phase rotation angle.

Each symbol of symbol streams of frame-synchronizing signalsBPSK-demapped at the transmission side and demodulated into I and Qbase-band signals I(8) and Q(8) by the demodulating circuit 1 isdemapped to bit (0) or (1) by the BPSK demapper section 3. The phasedifference between a symbol demapped to bit (0) and a symbol demapped tobit (1) is equal to 180°. Therefore, by rotating symbols to be demappedto bit (1) of a frame-synchronizing-signal portion of a received symbolstream by 180°, symbol streams to be all demapped to bit (0) areobtained.

Moreover, by obtaining the average value of a plurality of symbols ofthe symbol stream to be all demapped to bit (0), a received-signal-pointarrangement for bit (0) of BPSK is obtained. Therefore, by obtaining thephase difference between an obtained received-signal point for bit (0)of BPSK and a signal point arrangement “0” demapped to bit (0) at thetransmission side, assuming the phase difference as areceived-signal-phase rotation angle Θ and applying phase rotation ofη=−Θ to all I and Q base-band signals, it is possible to generateabsolute phases of I and Q base-band signals I(8) and Q(8).

As described above, the frame-synchronizing-signal generator 6 generatesa bit stream same as the pattern SYNCPAT of an acquiredframe-synchronizing pulse by receiving the frame-synchronizing pulseoutput from the frame-synchronizing circuit 5 and supplies the bitstream to the 0°/180° phase-rotating circuit 83 of thereceived-signal-phase rotation angle detecting circuit 8 as aregenerated frame-synchronizing signal. The 0°/180° phase-rotatingcircuit 83 rotates phases of I and Q base-band signals by 180° when abit in a bit stream of a supplied regenerated frame-synchronizing signalis bit (1) but the circuit 83 does not rotate the phases in the case ofbit (0).

The timing of a bit stream of a regenerated frame-synchronizing signaltransmitted from the frame-synchronizing-signal generator 6 and that ofa symbol stream of a frame-synchronizing signal in I and Q symbolstreams are made to coincide with each other by the delay circuits 81and 82 at the input side of the 0°/180° phase-rotating circuit 83. Thedelay circuits 81 and 82 open their output gates only while aframe-synchronizing-signal-interval signal is output from theframe-synchronizing-signal generator 6. Therefore, I and Q symbolstreams DI(8) and DQ(8) of a frame-synchronizing-signal portion areoutput from the delay circuits 81 and 82. In case of the I and Q symbolstreams DI(8) and DQ(8), a symbol portion corresponding to bit (1) in abit stream of a regenerated frame-synchronizing signal is phase-rotatedby 180° in the 0°/180° phase-rotating circuit 83 but a symbol portioncorresponding to bit (0) is transmitted to the averaging circuits 85 and86 as symbol streams VI(8) and VQ(8) without any phase rotation. Thesymbol streams VI(8) and VQ(8) serve as symbol streams at the time ofreceiving a signal BPSK-demapped at the transmission side because it isjudged that 20 bits configuring a frame-synchronizing signal are all setto bit (0).

FIG. 28(A) shows a signal point arrangement of I and Q symbol streamsI(8) and Q(8) of a frame-synchronizing signal at the time of beingreceived at a received-signal-phase rotation angle of Θ=0 and FIG. 28(B)shows signal point arrangements of I and Q symbol streams VI(8) andVQ(8) after converted by the 0°/180° phase-rotating circuit 83. The Iand Q symbol streams VI(8) and VQ(8) are transmitted to the averagingcircuits 85 and 86 and, for example, each quantization bit length of thestreams is converted into approx. 16 to 18 bits, and thereafter, fourframes (16×4=64 symbols) of them are averaged and the average value ofthe four frames is output as AVI(8) and AVQ(8) according to thequantization bit length of original 8 bits. In this case, I and Q symbolstreams VI(8) and VQ(8) are averaged so that a signal point arrangementcan be stably obtained even if a slight phase change or amplitudefluctuation of a received base-band signal occurs due to deteriorationof a received C/N.

A received-signal point [AVI(8), AVQ(8)] of a signal obtained byBPSK-mapping bit (1) can be obtained by the averaging circuits 85 and86. Then, the received-signal point [AVI(8), AVQ(8)] is input to thephase judging circuit 87 comprising a ROM, a received-signal-phaserotation angle Θ is obtained in accordance with a received-signalphase-rotation-angle judging table on the AVI-AVQ phase plane shown inFIG. 29, and a three-bit phase-rotation-angle signal AR(3) of three bits(natural binary number) corresponding to Θ is output. “R=0-7” in FIG. 29denotes a decimal notation of a phase-rotation-angle signal AR(3). Forexample, “Θ=0” denotes a received-signal-phase rotation angle obtainedby judging a signal point Z=[AVI(8), AVQ(8)] shown in FIG. 29 inaccordance with a received-signal-phase rotation angle judging table.Therefore, R=0 is obtained and (000) is transmitted as thereceived-signal-phase rotation angle signal AR(3). When areceived-signal-phase rotation angle Θ is equal to π/4, R becomes equalto 1 and (001) is transmitted as the received-signal-phase rotationangle signal AR(3).

Absolute-phase generation is realized when the remapper 7 comprising aROM receives the received-signal-phase rotation angle signal AR(3) andphase-rotates I and Q base-band signals I(8) and Q(8) in accordance withthe received-signal-phase rotation angle signal AR(3).

Then, functions of the remapper 7 will be described below. The remapper7 configures a phase conversion circuit for making a signal pointarrangement of received I and Q base-band signals I(8) and Q(8) same asthat of the transmission side. A received-signal-phase rotation angle Θis calculated by the received-signal-phase rotation angle detectingcircuit 8 and the received-signal-phase rotation angle signal AR(3)corresponding to the received-signal-phase rotation angle Θ is suppliedto the remapper 7. In this case, the decimal notation R of thereceived-signal phase-rotation-angle signal AR(3) is an integer of 0 to7 and the relation with the received-signal-phase rotation angle Θ isdefined as shown by the following expression (1).

R=Θ/(π/4)  (1)

Where

Θ=m·(π/4)

m: integer of 0 to 7

Absolute phase generation for I and Q base-band signals can be realizedby applying reverse rotation, that is, phase rotation of −Θ to thereceived-signal-phase rotation angle Θ. Therefore, the remapper 7rotates phases of input I and Q base-band signals I and Q by an angleη(=−Θ) in accordance with the following expressions (2) and (3) andoutputs absolute-phase-generated I and Q base-band signals I′(8) andQ′(8) (hereafter also referred to as I′ and Q′ by omitting the number ofquantization bits).

I′=I cos(η)−Q sin(η)  (2)

Q′=I sin(η)+Q cos(η)  (3)

In case of the above conventional received-signal-phase rotation angledetecting circuit, however, when configuring the 0°/18° phase-rotatingcircuit 83 through table conversion, the memory capacity requires 128Kbytes (=2¹⁶×16 bits). Moreover, when configuring a phase discriminatingcircuit 86 through table conversion, the memory capacity requires 2¹⁶×3bits and thereby, a problem occurs that the circuit greatly increases insize.

It is an object of the present invention to provide an apparatus forgenerating an absolute phase of a signal received by a receiverrequiring only a small circuit size.

DISCLOSURE OF THE INVENTION

The apparatus for generating an absolute phase of a signal received by areceiver according to claim 1 of the present invention uses a receivercomprising demodulating means for demodulating a signal to bePSK-modulated in which at least 8PSK-modulated digital signal among8PSK-modulated digital signal, QPSK-modulated digital signal and aBPSK-modulated digital signal is time-multiplexed with a BPSK-modulatedframe-synchronizing signal, by using carrier waves regenerated bycarrier-wave regenerating means and outputting I and Q symbol-streamdata; frame-synchronizing-signal acquiring means for acquiring aframe-synchronizing signal from the demodulated I and Q symbol-streamdata; received-signal-phase rotation angle detecting means for detectinga phase rotation angle of I and Q symbol-stream data output from thedemodulating means against the transmission side; and antiphase rotatingmeans for antiphase-rotating a phase of I and Q symbol-stream dataoutput from the demodulating means by a phase rotation angle detected bythe received-signal-phase rotation angle detecting means so that thecarrier-wave regenerating means of the demodulating means has a phaseerror table storing carrier-wave phase error data for variousdemodulated I and Q symbol-stream data sets for each modulation system,reads phase error data corresponding to the demodulated I and Qsymbol-stream data from a phase error table of a correspondingmodulation system while the demodulating means demodulates a certainmodulation-system portion under normal reception, and corrects a phaseof a carrier wave; characterized in that the received-signalphase-rotation-angle detecting means includes phase-error data readingmeans for reading high-order bits for judging whether the absolute valueof a phase error is larger or smaller than (π/8)+s·(π/4) (s is 0 or 1)among phase error data corresponding to the demodulated I and Qsymbol-stream data from a phase error table for BPSK modulation of thecarrier-wave regenerating means and discriminating means fordiscriminating a phase rotation angle of a symbol portion correspondingto bit (0) (or bit (1)) of a frame-synchronizing signal against thetransmission side in I and Q symbol-stream data output from demodulatingmeans in accordance with the sign bit data of I (or Q) symbol-streamdata of a portion corresponding to bit (0) (or bit (1)) of aframe-synchronizing signal acquired by the frame-synchronizing-signalacquiring means in demodulated I and Q symbol-stream data and phaseerror data read by the phase error data reading means correspondingly tothe portion and outputting a discrimination result.

A received-signal-phase rotation angle is univocally determined inaccordance with a high-order bit for judging whether the absolute valueof a phase error in phase error data according to a phase error tablefor BPSK modulation corresponding to demodulated I and Q symbol-streamdata is larger or smaller than (π/8)+s·(π/4) (s is 0 or 1) and sign bitdata of I (or Q) symbol-stream data of a portion corresponding to bit(0) (or bit (1)) of a frame-synchronizing signal and can be identifiedthrough a simple operation. Therefore, it is unnecessary to use alarge-scale ROM dedicated for discrimination of a phase rotation angleand thereby, it is possible to decrease a circuit size.

The apparatus for generating an absolute phase of a signal received by areceiver according to claim 2 of the present invention uses a receivercomprising demodulating means for demodulating a signal to bePSK-modulated in which at least 8PSK-modulated digital signal and aQPSK-modulated digital signal among 8PSK-modulated digital signal,QPSK-modulated digital signal, and BPSK-modulated digital signal aretime-multiplexed with a BPSK-modulated frame-synchronizing signal, byusing carrier waves regenerated by carrier-wave regenerating means andoutputting I and Q symbol-stream data; frame-synchronizing-signalacquiring means for acquiring a frame-synchronizing signal from thedemodulated I and Q symbol-stream data; received-signal-phase rotationangle detecting means for detecting a phase rotation angle of I and Qsymbol-stream data output from the demodulating means against thetransmission side; and antiphase rotating means for antiphase-rotatingand outputting a phase of I and Q symbol-stream data output from thedemodulating means by a phase rotation angle detected by thereceived-signal-phase rotation angle detecting means so that thecarrier-wave regenerating means of the demodulating means has a phaseerror table storing carrier-wave phase error data for variousdemodulated I and Q symbol-stream data sets for each modulation system,reads phase error data corresponding to the demodulated I and Qsymbol-stream data by referring to a phase error table of acorresponding modulation system while the demodulating means demodulatesa certain modulation-system portion under normal reception, and correctsa phase of a carrier wave; characterized in that thereceived-signal-phase rotation angle detecting means includesphase-error data reading means for reading high-order bits for judgingwhether the absolute value of a phase error is larger or smaller thanπ/8 among phase error data corresponding to the demodulated I and Qsymbol-stream data out of a phase error table for QPSK modulation of thecarrier-wave regenerating means and discriminating means fordiscriminating a phase rotation angle of a symbol portion correspondingto bit (0) (or bit (1)) of a frame-synchronizing signal against thetransmission side in I and Q symbol-stream data in accordance with thesign bit data of I and Q symbol-stream data of a portion correspondingto bit (0) (or bit (1)) of a frame-synchronizing signal acquired by theframe-synchronizing-signal acquiring means and phase error data read bythe phase error data reading means correspondingly to the portion andoutputting a discrimination result.

A received-signal-phase rotation angle is univocally determined inaccordance with a high-order bit for judging whether the absolute valueof a phase error in phase error data according to a phase error tablefor QPSK modulation corresponding to demodulated I and Q symbol-streamdata is larger or smaller than π/8 and sign bit data of I and Qsymbol-stream data of a portion corresponding to bit (0) (or bit (1)) ofa frame-synchronizing signal and can be identified through a simpleoperation. Therefore, it is unnecessary to use a large-scale ROMdedicated to discrimination of a phase rotation angle and thereby, it ispossible to decrease a circuit size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of an essentialportion of a wave to be PSK-modulated receiver of a first embodiment ofthe present invention;

FIGS. 2A and 2B are illustrations showing relations betweenreceived-signal-phase rotation angle signals output by aphase-rotation-angle discriminating circuit in FIG. 1 andreceived-signal-phase rotation angles;

FIG. 3 is a block diagram showing a configuration of an averagingcircuit in FIG. 1;

FIGS. 4A and 4B are illustrations showing relations between binary codesand gray codes;

FIG. 5 is a block diagram showing a configuration of an essentialportion of a wave to be PSK-modulated receiver of a second embodiment ofthe present invention;

FIG. 6 is an illustration showing relations between inputs and outputsof a binary converter in FIG. 5;

FIG. 7 is a block diagram showing a configuration of an essentialportion of a wave-to-be-PSK-modulated receiver of a third embodiment ofthe present invention;

FIG. 8 is a block diagram showing a configuration of an essentialportion of a wave to be PSK-modulated receiver of a modification;

FIG. 9 is a block diagram showing a configuration of an essentialportion of a wave to be PSK-modulated receiver of another modificationin FIG. 7;

FIG. 10 is a block diagram showing a configuration of an essentialportion of a wave to be PSK-modulated receiver of a modification in FIG.8;

FIGS. 11A and 11B are illustrations showing a frame configuration of ahierarchical transmission system;

FIG. 12 is a block diagram showing a configuration around a demodulatingcircuit of a wave to be PSK-modulated receiver according to aconventional hierarchical transmission system;

FIGS. 13A to 13C are illustrations showing signal point arrangements forPSK mapping;

FIG. 14 is a block diagram of a locally-omitted carrier-waveregenerating circuit in FIG. 12;

FIG. 15 is an illustration showing how to measure a phase of areceived-signal point;

FIG. 16 is an illustration showing how to measure areceived-signal-phase rotation angle;

FIG. 17 is an illustration showing a phase error table for 8PSK;

FIG. 18 is an illustration showing a phase error table for QPSK;

FIG. 19 is an illustration showing a phase error table for QPSK;

FIG. 20 is an illustration showing a phase error table for BPSK;

FIG. 21 is an illustration showing a phase error table for BPSK;

FIG. 22 is an illustration showing a phase error table for BPSK;

FIG. 23 is an illustration showing a phase error table for BPSK;

FIG. 24 is a block diagram of a sync detecting/regenerating circuit inFIG. 12;

FIGS. 25A and 25B are illustrations for explaining BPSK demapping;

FIG. 26 is a circuit diagram showing a configuration of a sync detectingcircuit in FIG. 24;

FIG. 27 is a circuit diagram showing a configuration of a BPSK demapperin FIG. 24;

FIGS. 28A and 28B are signal point arrangement diagrams of aframe-synchronizing signal before and after passing through a 0°/180°phase-rotating circuit in FIG. 12; and

FIG. 29 is an illustration of a received-signal-phase rotation anglediscriminating table used by a phase judging circuit in FIG. 12.

BEST MODE FOR CARRYING OUT THE INVENTION

Then, a first embodiment of the present invention will be describedbelow by referring to FIG. 1.

FIG. 1 is a block diagram of an essential portion of a wave to bePSK-modulated receiver of the present invention, in which a componentsame as that in FIG. 12 is provided with the same symbol.

A selector 16A of a carrier-wave regenerating circuit 10A enables only aphase error table 13 for 8PSK (refer to FIG. 17) while a symbol clockCLK_(SYB) is activated (H-level zone of CLK_(SYB); refer to FIG. 11B)before a transmission-configuration identifying circuit 9 identifies amultiple configuration of a frame and a received-signal-phase rotationangle detecting circuit 8A detects a received-signal-phase rotationangle (Θ), reads phase error data Δφ(8) corresponding to I and Qsymbol-stream data I(8) and Q(8) output from a demodulating circuit 1Awhile the symbol clock CLK_(SYB) is activated, and outputs the dataΔφ(8) to a D/A converter 17. Moreover, at the same time as the above,the selector 16A enables only a phase error table 15-1 for BPSK (referto FIG. 20) while the symbol clock CLK_(SYB) is not activated (L-levelzone of CLK_(SYB); refer to FIG. 11B), reads high-order three bits(hereafter referred to as phase error data Δφ(3)} in the phase errordata Δφ(8) corresponding to I and Q symbol-stream data I(8) and Q(8)output from the demodulating circuit 1A, and outputs the high-orderthree bits to the received-signal-phase rotation angle detecting circuit8A while symbol clock CLK_(SYB) is not activated. It is known from thephase error data Δφ(3) whether the absolute value of an phase error islarger or smaller than (π/8)+s·(π/4) (s is 0 or 1).

After the transmission-configuration identifying circuit 9 identifies amultiple configuration of a frame and the received-signal-phase rotationangle detecting circuit 8A detects a received-signal-phase rotationangle (Θ), the selector 16A reads the phase error data Δφ(8)corresponding to I and Q symbol-stream data I(8) and Q(8) out of amodulation system of a received signal demodulated by the demodulatingcircuit 1A and a phase error table corresponding to thereceived-signal-phase rotation angle (Θ) while a symbol clock CLK_(SYB)is activated and outputs the data Δφ(8) to the D/A converter 17 andmoreover, reads the phase error data Δφ(3) of high-order three bits inthe phase error data Δφ(8) corresponding to I and Q symbol-stream dataI(8) and Q(8) out of the phase error table 15-1 for BPSK while thesymbol clock CLK_(SYB) is not activated.

Symbol 90 denotes a delay circuit for delaying phase error data Δφ(3)read by the selector 16A by a predetermined period and then outputtingthe data. The delay circuit 90 adjusts timing so that the phase errordata Δφ(3) corresponding to the first portion of a frame-synchronizingsignal in I symbol-stream data I(8) is output just when the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalfrom I and Q symbol-stream data I(8) and Q(8) and starts outputting aregenerated frame-synchronizing signal. Symbol 91 denotes a delaycircuit and delays sign-bit data i(1) serving as the MSB of an I symbolstream by a predetermined period and then outputs the data. The delaycircuit 91 adjusts timing so that sign-bit data i(1) of the firstportion of a frame-synchronizing signal in I symbol stream data I(8) isoutput just when the frame-sync detecting/regenerating circuit 2acquires a frame-synchronizing signal from I and Q symbol-stream dataI(8) and Q(8) and starts outputting a regenerated frame-synchronizingsignal.

Symbol 92 denotes a phase-rotation-angle discriminating circuit,discriminates a phase rotation angle against the transmission side abouta symbol portion corresponding to bit (1) of a frame-synchronizingsignal in I and Q symbol streams I(8) and Q(8) output from thedemodulating circuit 1A in accordance with a portion of an output ofdelay circuit 91 or 91 corresponding to the frame-synchronizing signal,moreover discriminates a phase rotation angle of a symbol portioncorresponding to bit (0) of a frame-synchronizing signal against thetransmission side and successively outputs a discrimination result.Symbol 93 in the phase-rotation-angle discriminating circuit 92 denotesa four-bit adder for adding four-bit data (however, carry to fifth bitis not performed), in which an output of the delay circuit 91 is inputto the most significant bit of one input side and an output of the delaycircuit 90 is input to low-order three bits. A selector 94 is connectedto the other input side of the adder 93. The selector 94 inputs a bitstream of a regenerated frame-synchronizing signal output from theframe-sync detecting/regenerating circuit 2, outputs A(4)=(0101) whenthe portion of bit (0) is input, and outputs B(4)=(1101) when theportion of bit (1) is input. The adder 93 outputs high-order three bitsof an addition result as a phase-rotation-angle signal R(3).

Symbol 95 denotes an averaging circuit for averaging aphase-rotation-angle signal R(3). In this case, the averaging circuit 95averages frame-synchronizing signals for four frames and outputs anaveraged signal to the remapper 7 and selector 16A as anphase-rotation-angle signal AR(3). Examples of an averaging circuit 95will be described later.

Other portions are configured completely the same as those in FIG. 12.

Then, operations of the first embodiment are described below.

(1) Start of Reception

The selector 16A of the carrier-wave regenerating circuit 10A enablesonly the phase error table 13 for 8PSK while a symbol clock CLK_(SYB) isactivated before the transmission-configuration identifying circuit 9identifies a multiple configuration of a frame and thereceived-signal-phase rotation angle detecting circuit 8A detects areceived-signal-phase rotation angle after start of reception, reads thephase error data Δφ(8) corresponding to I and Q symbol stream data I(8)and Q(8) output from the demodulating circuit 1A while the symbol clockCLK_(SYB) is activated and outputs the data to the D/A converter 17.Moreover, at the same time as the above, the selector 16A enables onlythe phase error table 15-1 for BPSK while the symbol clock CLK_(SYB) isactivated, reads the phase error data Δφ(3) corresponding to I and Qsymbol-stream data I(8) and Q(8) output from the demodulating circuit 1Awhile the symbol clock CLK_(SYB) is not activated, and outputs the datato the delay circuit 90.

When the selector 16A outputs the phase error data Δφ(8) read out of thephase error table 13 for 8PSK to the D/A converter 17, the data isconverted into a phase error voltage by the D/A converter 17 and then,low-frequency components are eliminated from the phase error voltage byan LPF 18 and the voltage is applied to a VCO 11 as a control voltage.When the phase error data Δφ(8) is equal to 0, outputs of the LPF 18 arenot changed or phases of reference carrier waves f_(c1) and f_(c2) arenot changed. However, when the phase error data Δφ(8) is positive, anoutput of the LPF 18 increases and phases of the reference carrier wavesf_(c1) and f_(c2) are delayed. When the phase error data Δφ(8) isnegative, an output of the LPF 18 decreases and phases of the referencecarrier waves f_(c1) and f_(c2) are advanced. Thereby, phases of thereference carrier waves f_(c1) and f_(c2) are corrected so as to keep acertain relation with a phase of a received carrier wave. As a result,the demodulating circuit 1A corrects digital signals of signal pointarrangements “0” to “7” of phases 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4,and 7π/4 to positions rotated by Θ=m×π/4 (m is any one of integers 0 to7) on I-Q phase plane at the reception side.

Moreover, in the phase error table 15-1, the phase error data Δφ(3) ofhigh-order three bits of the phase error data Δφ(8) corresponding to Iand Q symbol-stream data I(8) and Q(8) denote the number of bits forjudging whether an absolute value of a phase error is larger or smallerthan (π/8)+s·(π/4) (s is 0 or 1) (refer to FIG. 20). By combining theΔφ(3) and the sign bit data i(1) serving as the MSB of I symbol-streamdata I(8) and applying a simple operation to the combination of theΔφ(3) and I(8), it is possible to identify to which signal pointarrangement a received-signal point corresponds among eight signal-pointarrangements “0” to “7”. Because a signal point arrangement of theportion of bit (0) (or bit (1)) of a frame-synchronizing signal at thetransmission side is determined as “0” (or “4”), a received-signal-phaserotation angle is univocally obtained from the Δφ(3) and the sign bitdata serving as the MSB of I symbol-stream data.

When the delay circuits 90 and 91 delay the phase error data Δφ(3)output from the selector 16A and the sign bit data i(1) of Isymbol-stream data I(8) fetched from an output of the demodulatingcircuit 1 and the frame-sync detecting/regenerating circuit 2 acquires aframe-synchronizing signal from I and Q symbol-stream data and startsoutputting a regenerated frame-synchronizing signal, thereceived-signal-phase rotation angle detecting circuit 8A first adjuststiming so that the phase error data Δφ(3) corresponding to the head ofthe frame-synchronizing-signal portion of I symbol-stream data I(8) isoutput from the delay circuit 90 and the sign bit data i(1)corresponding to the head of the frame-synchronizing-signal portion of Isymbol-stream data I(8) is output from the delay circuit 91. Outputs ofthe delay circuits 90 and 91 are input to one input side of the adder 93as a high-order bit and a low-order bit.

When a certain time elapses after start of reception, the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalin I and Q symbol streams I(8) and Q(8) and outputs a regeneratedframe-synchronizing signal. Then, the selector 94 selects A(4)=(0101) atthe portion of bit (0) of the regenerated frame-synchronizing signal tooutput it and selects B(4)=(1101) at the portion of bit (1) to outputit. The adder 93 adds one input and the other input at each bit positionof the 20-bit regenerated frame-synchronizing signal to outputhigh-order three bits. Then, the adder 93 outputs areceived-signal-phase rotation angle signal R(3) obtained by expressingR with a three-bit natural binary number at the time of dividing areceived-signal-phase rotation angle Θ into 0, π/4, 2π/4, 3π/4, 4π/4,5π/4, 6π/4, and 7π/4 and relating them to R=0 to 7 of decimal notation(refer to FIG. 2B).

The averaging circuit 95 captures outputs of the adder 93 while itreceives frame-synchronizing-signal-interval signals from the frame-syncdetecting/regenerating circuit 2. Then, for example, the circuit 95averages outputs for four frames and outputs the averaging result to theremapper 7 as a received-signal-phase rotation angle signal AR(3) tomake the remapper 7 generate an absolute phase. Moreover, the circuit 95outputs the received-signal-phase rotation angle AR(3) to the selector16A. Received-signal-phase rotation angle signals R(3) are averaged inorder to stably obtain a received-signal-phase rotation angle even if aslight phase change or amplitude fluctuation occurs in a receivedbase-band signal due to deterioration of a received C/N.

FIG. 3 shows an example of the averaging circuit 95. Thereceived-signal-phase rotation angle signal R(3) output from the adder93 is converted into a three-bit gray code by a gray code converter 96in accordance with FIG. 4A. A gray code has a characteristic that onlyone bit position changes between adjacent codes. Majority-decisionjudging circuits 97-1 to 97-3 are provided for bit positions G0 to G2 atthe output side of the gray code converter 96 to determine which bit ismore output from the gray code converter 96, bit (1) or bit (0) whileframe-synchronizing-signal-interval signals are input for four frames.Outputs F0 to F2 of the majority-decision judging circuits 97-1 to 97-3are input to a binary code converter 98 in which conversion reverse tothe conversion by the gray code converter 96 is performed in accordancewith FIG. 4B. An output of the binary code converter 98 is output as thereceived-signal-phase rotation angle signal AR(3).

It is also possible to perform majority-decision judgment by omittingthe gray code converter 96 and binary code converter 98 and directlyinputting outputs of the adder 93 to the majority-decision judgingcircuits 97-1 to 97-3. However, by performing gray-coding, even if aphase shown by the received-signal-phase rotation angle signal R(3)changes by π/4 code, change always occurs at only one bit position or,even if a slight phase change or amplitude change occurs in a receivedbase-band signal due to deterioration of a received C/N and thereceived-signal-phase rotation angle signal R(3) erroneously shifts byπ/4, it is possible to minimize the influence and thus, the reliabilityis improved.

(2) Normal Receiving Operation

When the frame-sync detecting/regenerating circuit 2 acquires aframe-synchronizing signal, the transmission-configuration identifyingcircuit 9 immediately identifies a multiple configuration and outputs amodulation-system identifying signal DM showing to whichmodulation-system portion the present I and Q symbol streams output fromthe demodulating circuit 1A correspond to the selector 16A or the like.

The selector 16A receiving the received-signal-phase rotation anglesignal AR(3) from the averaging circuit 95 enables only the phase errortable 13 while the demodulating circuit 1A demodulates an8PSK-modulation-system portion and a symbol clock CLK_(SYB) is activatedwhen a received-signal-phase rotation angle Θ shown by thereceived-signal-phase rotation angle signal AR(3) is equal to, forexample, 3π/4 by using the modulation-system identifying signal DM inputfrom the transmission-configuration identifying circuit 9 and readsphase error data Δφ(8) corresponding to I and Q symbol-stream data I(8)and Q(8) output from the demodulating circuit 1A while the symbol clockCLK_(SYB) is activated to output the data Δφ(8) to the D/A converter 17.As a result, phases of the reference carrier waves f_(c1) and f_(c2) arecorrected so that digital signals (abc) 8PSK-mapped to transmission-sidesignal-point arrangements “0”, “1”, “2”, “3”, “4”, “5”, “6”, and “7”appear on reception-side signal point arrangements “3,” “4”, “5”, “6”,“7”, “0”, “1”, and “2” independently of phase change of the receivedcarrier waves.

Because phases of I and Q symbol-stream data I(8) and Q(8) of the8PSK-modulation-system portion output from the demodulating circuit 1Aare rotated by the remapper 7 by η=−Θ=−3π/4, received-signal points of Iand Q symbol-stream data I′(8) and Q′(8) output from the remapper 7coincide with those of the transmission side.

When Θ is equal to 3π/4, the selector 16A enables only the phase errortable 14-2 while the demodulating circuit 1A demodulates aQPSK-modulation-system portion and a symbol clock CLK_(SYB) is activatedand reads from the phase error table 14-2 (refer to FIG. 19) the phaseerror data Δφ(8) corresponding to I and Q symbol-stream data I(8) andQ(8) output from the demodulating circuit 1A while the symbol clockCLK_(SYB) is activated to output the data Δφ(8) to the D/A converter 17.As a result, phases of the reference carrier waves f_(c1) and f_(c2) arecorrected so that digital signals (de) QPSK-mapped to transmission-sidesignal point arrangements “1”, “3”, “5”, and “7” appear onreception-side signal point arrangements “4”, “6”, “0”, and “2” andtherefore, the phases are kept at a phase rotation angle equal to areceived-signal-phase rotation angle by 8PSK. Because phases of I and Qsymbol-stream data I(8) and Q(8) of the QPSK-modulation-system portionoutput from the demodulating circuit 1A are also rotated by the remapper7 by η=−Θ=−3π/4, received-signal points of I and Q symbol-stream dataI′(8) and Q′(8) output from the remapper 7 coincide with those of thetransmission side.

When Θ is equal to 3π/4, the selector 16A enables only the phase errortable 15-3 (refer to FIG. 22) while the demodulating circuit 1Ademodulates a BPSK-modulation-system portion and a symbol clockCLK_(SYB) is activated and reads from the phase error table 15-3 thephase error data Δφ(8) corresponding to I and Q symbol-stream data I(8)and Q(8) output from the demodulating circuit 1A while the symbol clockCLK_(SYB) is activated to output the data Δφ(8) to the D/A converter 17.As a result, phases of the reference carrier waves f_(c1) and f_(c2) arecorrected so that digital signals (f) BPSK-mapped to transmission-sidesignal point arrangements “0” and “4” appear on reception-side signalpoint arrangements “3” and “7” and therefore, the phases are kept at aphase rotation angle equal to a received-signal-phase rotation angle by8PSK. Because phases of I and Q symbol-stream data I(8) and Q(8) of theBPSK-modulation-system portion output from the demodulating circuit 1Aare also rotated by the remapper 7 by η=−Θ=−3π/4, received-signal pointsof I and Q symbol-stream data I′(8) and Q′(8) output from the remapper 7coincide with those of the transmission side.

Moreover, also under the normal receiving operation, the selector 16Aenables only the phase error table 15-1 while the symbol clock CLK_(SYB)is not activated and reads from the phase error table 15-1 the phaseerror data Δφ(3) corresponding to I and Q symbol-stream data I(8) andQ(8) output from the demodulating circuit 1A while the symbol clockCLK_(SYB) is not activated to output the data Δφ(3) to the delay circuit90. Then, the phase-rotation-angle discriminating circuit 92discriminates a phase rotation angle in accordance with an output of thedelay circuit 90 or 91, outputs a discrimination result in the form ofthe received-signal-phase rotation angle signal R(3) and the averagingcircuit 95 averages discrimination results for four frames and outputsthe averaged signal R(3) as the received-signal-phase rotation anglesignal AR(3). When a received-signal-phase rotation angle Θ shown by theAR(3) is the same as ever, a phase rotation angle of the remapper 7 isnot changed or a phase error table to be selected by the selector 16A isnot changed. However, the received-signal-phase rotation angle Θ ischanged from ever, the remapper 7 phase-rotates by −Θ from a new Θ.Moreover, the selector 16A changes a phase error table to be selected inaccordance with the change of Θ.

According to this embodiment, a rotation angle of I and Q symbol-streamdata I(8) and Q(8) of a portion corresponding to bit (1) (bit (0)) of aframe-synchronizing signal is discriminated in accordance withhigh-order three bits for judging whether the absolute value of an phaseerror in phase error data according to a phase error table for BPSKmodulation corresponding to I and Q symbol-stream data of a portioncorresponding to bit (1) (bit (0)) of a demodulated frame-synchronizingsignal is larger or smaller than (π/8)+s·(π/4) (s is 0 or 1) and signbit data i(1) of I symbol-stream data. Therefore, it is possible todiscriminate a received-signal-phase rotation angle through a simpleoperation. Therefore, it is unnecessary to use a large ROM dedicated todiscrimination of a phase rotation angle and it is possible to decreasea circuit in size.

The above embodiment uses the sign bit data i(1) of I symbol-stream dataI(8). However, it is also permitted to use sign bit data serving as theMSB of Q symbol-stream data Q(8) instead. Moreover, it is permitted toread the phase error data Δφ(3) from one of the phase error tables 15-2,15-3, and 15-4 instead of reading the data Δφ(3) from the phase errortable 15-1. These changes can be performed only by properly changingvalues of A(4) and B(4) selected by the selector 94.

Moreover, though phase rotation angles of portions of bits (1) and (0)of a frame-synchronizing signal of I and Q symbol-stream data are bothdiscriminated, it is also permitted to discriminate either of the phaserotation angles. Furthermore, an averaging method can be optionallychanged by the averaging circuit 95. Therefore, it is also permitted toaverages discrimination results for only one frame or two frames oraverage one bit or a plurality of bits at a specific position orpositions of a frame-synchronizing signal for a plurality of frames.

Then, a second embodiment of the present invention will be describedbelow by referring to FIG. 5.

FIG. 5 is a block diagram of an essential portion of a wave to bePSK-modulated receiver of the present invention, in which a componentsame as that in FIG. 1 is provided with the same symbol.

In case of the embodiment shown in FIG. 1, phase error data Δφ(3) isread out of the phase error table 15-1 for BPSK. In case of FIG. 5,however, phase error data Δφ(3) is read out of a phase error table 14-1for QPSK (refer to FIG. 18).

A selector 16B of a carrier-wave regenerating circuit 10B enables only aphase error table 13 for 8PSK while a symbol clock CLK_(SYB) isactivated before a transmission-configuration identifying circuit 9identifies a multiple configuration of a frame and areceived-signal-phase rotation angle detecting circuit 8B detects areceived-signal-phase rotation angle and reads phase error data Δφ(8)corresponding to I and Q symbol-stream data I(8) and Q(8) output from ademodulating circuit 1A while the symbol clock CLK_(SYB) is activated tooutput the data Δφ(8) to a D/A converter 17. Moreover, at the same timeas the above, the selector 16B enables only the phase error table 14-1for QPSK while the symbol clock CLK_(SYB) is not activated and readsfrom the phase error table 14-1 phase error data Δφ(3) of high-orderthree bits in the phase error data Δφ(8) corresponding to I and Qsymbol-stream data I(8) and Q(8) output from the demodulating circuit 1Awhile the symbol clock CLK_(SYB) is not activated to output the dataΔφ(3) to the received-signal-phase rotation angle detecting circuit 8B.It is known in accordance with the phase error data Δφ(3) whether theabsolute value of a phase error is larger or smaller than π/8.

After the transmission-configuration identifying circuit 9 identifies amultiple configuration of a frame and the received-signal-phase rotationangle detecting circuit 8B detects a received-signal-phase rotationangle Θ, the selector 16B reads phase error data Δφ(8) corresponding toI and Q symbol-stream data I(8) and Q(8) in accordance with a modulationsystem of a received signal demodulated by the demodulating circuit 1Band a phase error table corresponding to the received-signal-phaserotation angle Θ to output the data Δφ(8) to the D/A converter 17 andmoreover, reads from the phase error table 14-1 for QPSK phase errordata Δφ(3) corresponding to I and Q symbol-stream data I(8) and Q(8)while the symbol clock CLK_(SYB) is not activated to output the dataΔφ(3) to the received-signal-phase rotation angle detecting circuit 8B.

Symbol 90 denotes a delay circuit for delaying phase error data Δφ(3)read by the selector 16B by a predetermined period and then outputtingthe data. The delay circuit 90 adjusts timing so that phase error dataΔφ(3) corresponding to the first portion of a frame-synchronizing signalof I symbol stream data I(8) is output just when a frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalfrom I and Q symbol-stream data I(8) and Q(8) and starts outputting aregenerated frame-synchronizing signal. Symbol 91 denotes a delaycircuit for delaying sign bit data i(l) serving as the MSB of I symbolstream by a predetermined period and then outputting the data. The delaycircuit 91 adjusts timing so that the sign bit data i(1) at the firstportion of a frame-synchronizing signal of I symbol-stream data I(8) isoutput just when the frame-sync detecting/regenerating circuit 2acquires a frame-synchronizing signal from I and Q symbol-stream dataI(8) and Q(8) and starts outputting a regenerated frame-synchronizingsignal.

Symbol 99 denotes a delay circuit for delaying sign bit data q(1)serving as the MSB of Q symbol-stream data Q(8) by a predeterminedperiod and then outputting the data. The delay circuit 99 adjusts timingso that sign bit data q(1) at the first portion of a frame-synchronizingsignal of Q symbol-stream data Q(8) is output just when the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalfrom I and Q symbol-stream data I(8) and Q(8) and starts outputting aregenerated frame-synchronizing signal.

Symbol 92B denotes a phase-rotation-angle discriminating circuit fordiscriminating a phase rotation angle of a symbol portion correspondingto bit (1) of a frame-synchronizing signal in I and Q symbol streamsI(8) and Q(8) output from the demodulating circuit 1B against thetransmission side from a portion of an output of the delay circuit 90,91, or 99 corresponding to a frame-synchronizing signal and moreover,discriminating a phase rotation angle of a symbol portion of aframe-synchronizing signal corresponding to bit (0) against thetransmission side to successively output discrimination results. In thephase-rotation-angle discriminating circuit 92, symbol 100 denotes athree-bit adder for adding three-bit data (however, carry to fourth bitis not performed), which adds an output of the delay circuit 90 andC(3)=(110) and outputs low-order 2 bits.

Symbol 101 denotes a binary converter which converts two-bit dataobtained by combining an output of the delay circuit 99 as a high-orderbit with an output of the delay circuit 91 as a low-order bit into abinary code in accordance with FIG. 6 and outputs the code. Symbol 102denotes a four-bit adder for adding four-bit data (however, carry tofifth bit is not performed), in which an output of the converter 101 isinput to high-order two bits at one input side and low-order two bits ofan addition result by the adder 100 is input to low-order two bits atthe one input side. A selector 103 is connected to the other input sideof the adder 102, which inputs a bit stream of a regeneratedframe-synchronizing signal output from the frame-syncdetecting/regenerating circuit 2, outputs D(4)=(1111) when the portionof bit (0) is input, and outputs E(4)=(0111) when the portion of bit (1)is input. The adder 102 outputs high-order three bits of an additionresult as a received-signal-phase rotation angle signal R(3).

Symbol 95 denotes an averaging circuit for averagingreceived-signal-phase rotation angle signals R(3). In this case, forexample, the averaging circuit 95 averages frame-synchronizing signalsfor four frames and outputs the averaged signal to the remapper 7 andselector 16B as a received-signal-phase rotation angle signal AR(3).Other portions are configured completely the same as those in FIG. 1are.

Then, operations of the second embodiment are described below.

(1) Start of Reception

The selector 16B of the carrier-wave regenerating circuit 10B enablesonly the phase error table 13 for 8PSK while a symbol clock CLK_(SYB) isactivated before the transmission-configuration identifying circuit 9identifies a multiple configuration of a frame and thereceived-signal-phase rotation angle detecting circuit 8B detects areceived-signal-phase rotation angle and reads from the phase errortable 13 phase error data Δφ(8) corresponding to the set data of I and Qsymbol-stream data I(8) and Q(8) output from the demodulating circuit 1Bwhile the symbol clock CLK_(SYB) is activated to output the data Δφ(8)to the D/A converter 17. Moreover, at the same time as the above, theselector 16B enables only the phase error table 14-1 for QPSK while thesymbol clock CLK_(SYB) is not activated and reads out of the phase errortable 14-1 phase error data Δφ(3) of high-order three bits in phaseerror data Δφ(8) corresponding to the set data of I and Q symbol-streamdata I(8) and Q(8) output from the demodulating circuit 1B while thesymbol clock CLK_(SYB) is not activated to output the data Δφ(3) to thedelay circuit 90.

Because the selector 16B reads the phase error data Δφ(8) out of thephase error table 13 for 8PSK and outputs the data to the D/A converter17, the demodulating circuit 1B corrects digital signals of signal pointarrangements “0” to “7” of phases 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4,and 7π/4 at the transmission side to positions rotated by Θ=m×π/4 (m isany one of integers 0 to 7) on the I-Q phase plane at the receptionside.

In the phase error table 14-1, high-order three bits Δφ(3) of phaseerror data Δφ(8) corresponding to I and Q symbol-stream data I(8) andQ(8) denote the number of bits for judging whether the absolute value ofa phase error is larger or smaller than π/8 (refer to FIG. 18). Bycombining the Δφ(3) with sign bit data i(1) and q(1) serving as the MSBsof I and Q symbol-stream data I(8) and Q(8) and performing a simpleoperation, it is possible to discriminate to which of eight signal pointarrangements “0” to “7” a received-signal point corresponds. Because thetransmission-side signal point arrangement of the portion of bit (0) (orbit (1)) of a frame-synchronizing signal is determined as “0” (or “4”),a received-signal-phase rotation angle is univocally obtained from Δφ(3)and sign bit data i(1) and q(1) of I and Q symbol-stream data I(8) andQ(8).

When the delay circuits 90, 91, 99 delay phase error data Δφ(3) outputfrom the selector 16B, sign bit data i(1) of I symbol stream data I(8)fetched from an output of the demodulating circuit 1, and sign bit dataq(1) of Q symbol stream data Q(8), and the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalfrom I and Q symbol-stream data and starts outputting a regeneratedframe-synchronizing signal, the received-signal-phase rotation angledetecting circuit 8B adjusts timings so that phase error data Δφ(3)corresponding to the head of a frame-synchronizing-signal portion of Isymbol stream data I(8) is output from the delay circuit 90, sign bitdata i(1) corresponding to the head of a frame-synchronizing signal of Isymbol stream data I(8) is output from the delay circuit 91, and signbit data q(1) corresponding to the head of a frame-synchronizing-signalportion of Q symbol-stream data Q(8) is output from the delay circuit99. Outputs of the delay circuits 99 and 91 are binary-converted andthen, input as high-order bits of one input of the adder 102. An outputof the delay circuit 90 is added with (3)=(110) by the adder 100 andthen input as low-order two bits of one input of the adder 102.

When a certain time elapses after start of reception, the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalof I and Q symbol streams I(8) and Q(8) and outputs a regeneratedframe-synchronizing signal. Then, the selector 103 selects D(4)=(1111)at the portion of bit (0) of the regenerated frame-synchronizing signaland outputs it, and moreover selects E(4)=(0111) at the portion of bit(1) and outputs it. The adder 102 adds one input with the other input ateach bit position of a 20-bit regenerated frame-synchronizing signal andoutputs high-order three bits. Then, the adder 102 outputs areceived-signal-phase rotation angle signal R(3) obtained by expressingR with a three-bit natural binary number at the time of dividing areceived-signal-phase rotation angle Θ into 0, π/4, π/4, 3π/4, 4π/4,5π/4, 6π/4, and 7π/4 as shown in FIG. 2A and relating it to R=0-7 ofdecimal notation (refer to FIG. 2B}.

The averaging circuit 95 captures outputs of the adder 102 whileinputting frame-synchronizing-signal-interval signals from theframe-sync detecting/regenerating circuit 2, averages the signals for 4frames similarly to the case of FIG. 1, and outputs an averaging resultto the remapper 7 as a received-signal-phase rotation angle signal AR(3)to make the remapper 7 generate an absolute phase. Moreover, theaveraging circuit 95 outputs the received-signal-phase rotation anglesignal AR(3) to the selector 16B.

(2) Normal Receiving Operation

Immediately after the frame-sync detecting/regenerating circuit 2acquires a frame-synchronizing signal, the transmission-configurationidentifying circuit 9 identifies a multiple configuration and outputs amodulation-system-identifying signal DM showing to whichmodulation-system portion the present I and Q symbol-streams I(8) andQ(8) output from the demodulating circuit 1B correspond to the selector16B or the like.

The selector 16B receiving the received-signal-phase rotation anglesignal AR(3) from the averaging circuit 95 enables only the phase errortable 13 while the demodulating circuit 1B demodulates the8PSK-modulation-system portion and a symbol clock CLK_(SYB) is activatedwhen a received-signal-phase rotation angle Θ shown by AR(3) is equalto, for example, 2π/4 by using a modulation-system identifying signal DMreceived from the transmission-configuration identifying circuit 9 andreads phase error data Δφ(8) corresponding to I and Q symbol-stream dataI(8) and Q(8) out of the phase error table 13 to output the data Δφ(8)to the D/A converter 17. As a result, phases of the reference carrierwaves f_(c1) and f_(c2) are corrected so that digital signals (abc)8PSK-mapped to transmission-side signal-point arrangements “0”, “1”,“2”, “3”, “4”, “5”, “6”, and “7” appear on reception-side signal pointarrangements “2”, “3”, “4”, “5”, “6”, “7”, “0”, and “1”, independentlyof phase change of the received carrier waves.

Because phases of I and Q symbol-stream data I(8) and Q(8) of the8PSK-modulation-system portion output from the demodulating circuit 1Bare rotated by the remapper 7 by η=−Θ=−2π/4, received-signal points of Iand Q symbol-stream data I′(8) and Q′(8) output from the remappercoincide with those of the transmission side.

When Θ is equal to 2π/4, the selector 16B enables only the phase errortable 14-1 while the demodulating circuit 1B demodulates aQPSK-modulation-system portion and a symbol clock CLK_(SYB) is activatedand reads from the phase error table 14-1 and reads the phase error dataΔφ(8) corresponding to I and Q symbol-stream data I(8) and Q(8) tooutput the data Δφ(8) to the D/A converter 17. As a result, phases ofthe reference carrier waves f_(c1) and f_(c2) are corrected so thatdigital signals (de) QPSK-mapped to transmission-side signal pointarrangements “1”, “3”, “5”, and “7” appear on reception-side signalpoint arrangements “3”, “5”, “7”, and “1”. Therefore, the signals areheld at the same phase rotation angle as the received-signal-phaserotation angle at 8PSK. Moreover, because phases of I and Qsymbol-stream data I(8) and Q(8) of the QPSK-modulation-system portionoutput from the demodulating circuit 1B are rotated by the remapper 7 byΘ=−Θ=−2π/4, received-signal points of I and Q symbol stream data I′(8)and Q′(8) output from the remapper 7 coincide with those of thetransmission side.

When Θ is equal to 2π/4, the selector 16B enables only a phase errortable 15-3 while the demodulating circuit 1B demodulates aBPSK-modulation-system portion and a symbol clock CLK_(SYB) is activatedand reads phase error data Δφ(8) corresponding to I and Q symbol-streamdata I(8) and Q(8) out of the phase error table 15-3 to output the dataΔφ(8) to the D/A converter 17. As a result, because phases of thereference carrier waves f_(c1) and f_(c2) are corrected so that digitalsignals (f) BPSK-mapped to transmission-side signal point arrangements“0” and “4” appear on reception-side signal point arrangements “2” and“6”, the signals are kept at the same phase angle as thereceived-signal-phase rotation angle at 8PSK. Moreover, because phasesof I and Q symbol-stream data I(8) and Q(8) at theBPSK-modulation-system portion output from the demodulating circuit 1Bare rotated by the remapper 7 by η=−Θ=−2π/4, received signal points of Iand Q symbol-stream data I′(8) and Q′(8) output from the remapper 7coincide with those of the transmission side.

Also under the normal receiving operation, the selector 16B enables onlythe phase error table 14-1 while the symbol clock CLK_(SYB) is notactivated and reads phase error data Δφ(3) corresponding to I and Qsymbol-stream data I(8) and Q(8) output from the demodulating circuit 1Bout of the phase error table 14-1 while the symbol clock CLK_(SYB) isnot activated to output the data Δφ(3) to the delay circuit 90. Then,the phase-rotation-angle discriminating circuit 92B discriminates aphase rotation angle in accordance with an output of the delay circuit90, 91, or 99 and outputs discrimination results in the form ofreceived-signal-phase rotation angle signals R(3), and the averagingcircuit 95 averages signals R(3) for four frames to output averagedsignals R(3) as received-signal-phase rotation angle signals AR(3). Whena received-signal-phase rotation angle Θ shown by AR(3) is the same asever, a phase rotation angle of the remapper 7 is not changed or a phaseerror table selected by the selector 16B is not changed. However, whenthe angle Θ is not the same as ever, the remapper 7 phase rotates by −Θfrom new Θ. Moreover, the selector 16B changes a phase error table to beselected in accordance with a change of Θ.

This embodiment discriminates a phase rotation angle of I and Qsymbol-stream data I(8) and Q(8) at a portion corresponding to bit (1)(bit (0)) of a frame-synchronizing signal in accordance with high-orderthree bits for judging whether the absolute value of a phase error islarger or smaller than π/8 in the phase error data according to thephase error table 14-1 for QPSK modulation corresponding to I and Qsymbol-stream data at a portion corresponding to bit (1) (bit (0)) of ademodulated frame-synchronizing signal and sign bit data i(1) and q(1)of I and Q symbol stream-data I(8) and Q(8). Therefore, it is possibleto discriminate a received-signal-phase rotation angle through a simpleoperation. Thus, it is unnecessary to use a large ROM dedicated todiscrimination of a phase rotation angle and it is possible to decreasea circuit in size.

Moreover, the above embodiment reads phase error data Δφ(3) out of thephase error table 14-1. However, it is also permitted to read the phaseerror data Δφ(3) out of a phase error table 14-2. This change can bemade by properly changing C(3) added by the adder 100 and D(4) and E(4)selected by the selector 103.

Moreover, though phase rotation angles of both the portions of bits (1)and (0) of a frame-synchronizing signal in I and Q symbol-stream dataI(8) and Q(8) are discriminated, it is also permitted to discriminateonly either of the phase rotation angles. Furthermore, an averagingmethod can be optionally changed. Therefore, it is permitted to averagediscrimination result for one frame or two frames or average one bit ora plurality of bits at a specific position or positions of aframe-synchronizing signal for a plurality of frames.

Then, a third embodiment of the present invention will be describedbelow by referring to FIG. 7.

FIG. 7 is a block diagram of an essential portion of a wave to bePSK-modulated receiver of the present invention, in which a componentsame as that in FIG. 1 is provided with the same symbol.

The first embodiment in FIG. 1 has seven phase error tables 13, 14-1 and14-2, and 15-1 to 15-4 in a carrier-wave regenerating circuit and inputsI and Q symbol-stream data I(8) and Q(8) output from a demodulatingcircuit. In FIG. 7, however, only three phase error tables 13, 14-1, and15-1 are used and I and Q symbol-stream data I′(8) and Q′(8) output froma remapper 7 are input. Moreover, the remapper 7 does not detect phaserotation of I and Q symbol-stream data I(8) and Q(8) output from ademodulating circuit before a received-signal-phase rotation angle isdetected by a received-signal-phase rotation angle detecting circuit butit directly outputs input data.

A selector 16C of a carrier-wave regenerating circuit 10C enables only aphase error table 13 for 8PSK while a symbol clock CLK_(SYB) isactivated before a transmission-configuration identifying circuit 9identifies a multiple configuration of a frame and areceived-signal-phase rotation angle detecting circuit 8C detects areceived-signal-phase rotation angle after start of reception and readsfrom the phase error table 13 phase error data Δφ(8) corresponding to Iand Q symbol-stream data I′(8) and Q′(8) output from the remapper 7while the symbol clock CLK_(SYB) is activated to output the data Δφ(8)to a D/A converter 17. Moreover, at the same time as the above, theselector 16C enables only the phase error table 15-1 for BPSK while thesymbol clock CLK_(SYB) is not activated and reads from the phase errortable 15-1 high-order three bits (hereafter referred to as phase errordata Δφ(3)) in phase error data Δφ(8) corresponding to I and Qsymbol-stream data I′(8) and Q′(8) output from the remapper 7 while thesymbol clock CLK_(SYB) is not activated to output the data Δφ(3) to adelay circuit 90 of the received-signal-phase rotation angle detectingcircuit 8C. It is known from the phase error data Δφ(3) whether theabsolute value of a phase error is larger or smaller than (π/8)+s·(π/4)(s is 0 or 1).

After the transmission-configuration identifying circuit 9 identifies amultiple configuration of a frame and the received-signal-phase rotationangle detecting circuit 8C detects a received-signal-phase rotationangle Θ, the selector 16C enables only one of the phase error tables 13,14-1, and 15-1 corresponding to a modulation system of a received signaldemodulated by a demodulating circuit 1C while the symbol clockCLK_(SYB) is activated and reads phase error data Δφ(8) corresponding toI and Q symbol-stream data I′(8) and Q′(8) output from the remapper 7while the symbol clock CLK_(SYB) is activated to output the data Δφ(8)to D/A converter 17. Moreover, the selector 16C enables only the phaseerror table 15-1 for BPSK while the symbol clock CLK_(SYB) is notactivated and reads out of the phase error table 15-1 phase error dataΔφ(3) of high-order three bits in phase error data Δφ(8) correspondingto I and Q symbol-stream data I′(8) and Q′(8) output from the remapper 7while the symbol clock CLK_(SYB) is not activated to output the dataΔφ(3) to a delay circuit 90.

Symbol 90 denotes a delay circuit for delaying phase error data Δφ(3)read by the selector 16C by a predetermined period and then outputtingthe data. The delay circuit 90 adjusts timing so that phase error dataΔφ(3) corresponding to the first portion of a frame-synchronizing signalof I symbol-stream data I′(8) is output just when a frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalfrom I and Q symbol-stream data I′(8) and Q′(8) output from the remapper7 and starts outputting a regenerated frame-synchronizing signal. Symbol91 denotes a delay circuit for delaying sign bit data i′(1) serving asthe MSB of I symbol-stream data I′(8) by a predetermined period and thenoutputting it. The delay circuit 91 adjusts timing so that sign bit datai′(1) at the first portion of a frame-synchronizing signal of Isymbol-stream data I′(8) is output just when the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalfrom I and Q symbol-stream data I′(8) and Q′(8) and starts outputting aregenerated frame-synchronizing signal.

Symbol 92 denotes a phase-rotation-angle discriminating circuit,discriminates a phase rotation angle against the transmission side abouta symbol portion corresponding to bit (1) of a frame-synchronizingsignal in I and Q symbol streams I′(8) and Q′(8) and moreoverdiscriminates a phase rotation angle against the transmission side abouta symbol portion corresponding to bit (0) of the frame-synchronizingsignal to successively output a discrimination result as areceived-signal-phase rotation angle signal R(3).

Symbol 95 denotes an averaging circuit for averagingreceived-signal-phase rotation angle signals R(3). In this case, as anexample, the averaging circuit 95 averages frame-synchronizing signalsfor four frames and outputs the averaging result as areceived-signal-phase rotation angle signal AR(3). Symbol 110 denotes athree-bit adder for adding the last received-signal-phase rotation anglesignal OR(3) held by a register 111 and this-time received-signal-phaserotation angle signal AR(3) every when the averaging circuit 95 outputsthe received-signal-phase rotation-angle signal AR(3) and outputting theaddition result to the remapper 7 and selector 16C as a newreceived-signal-phase rotation angle signal OR(3) (however, carry tofourth bit is not performed). Symbol 111 denotes a register for holdinga received-signal-phase rotation angle signal OR(3) output by the adder110. Operations of the adder 110 and register 111 are described later.

Other components are completely the same as those in FIG. 1.

Then, operations of the third embodiment will be described.

In this case, it is assumed that the register 111 is previously clearedto (000).

(1) Start of Reception

The remapper 7 does not perform phase rotation at start of reception butit directly outputs I and Q symbol streams I(8) and Q(8) received fromthe demodulating circuit 1C as I′(8) and Q′(8).

The selector 16C of the carrier-wave regenerating circuit 10C enablesonly the phase error table 13 for 8PSK while a symbol clock CLK_(SYB) isactivated before the transmission-configuration identifying circuit 9identifies a multiple configuration of a frame and thereceived-signal-phase rotation angle detecting circuit 8C detects areceived-signal-phase rotation angle after start of reception and readsfrom the phase error table 13 phase error data Δφ(8) corresponding to Iand Q symbol-stream data I′(8) and Q′(8) output from the remapper 7while the symbol clock CLK_(SYB) is activated to output the data Δφ(8)to the D/A converter 17. Moreover, at the same time as the above, theselector 16C enables only the phase error table 15-1 for BPSK while thesymbol clock CLK_(SYB) is not activated and reads from the phase errortable 15-1 phase error data Δφ(3) of high-order three bits in phaseerror data Δφ(8) corresponding to I and Q symbol-stream data I′(8) andQ′(8) output from the remapper 7 while the symbol clock CLK_(SYB) is notactivated to output the data Δφ(3) to the delay circuit 90.

Because the selector 16C reads phase error data Δφ(3) out of the phaseerror table 13 for 8PSK and outputs the data Δφ(3) to the D/A converter17, the demodulating circuit 1C corrects digital signals of signal pointarrangements “0” to “7” of phases 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4,and 7π/4 at the transmission side to positions rotated by Θ=m×π/4 (m isany one of integers 0 to 7) on the I-Q phase plane at the receptionside.

Moreover, in the phase error table 15-1, high-order three bits Δφ(3) ofphase error data Δφ corresponding to I and Q symbol-stream data I′(8)and Q′(8) denote the number of bits for judging whether the absolutevalue of a phase error is larger or smaller than (π/8)+s·(π/4) (s is 0or 1). By combining the phase error data Δφ(3) with sign bit data i′(1)serving as the MSB of I symbol-stream data I′(8) and performing a simpleoperation, it is possible to discriminate to which of eight signalarrangements “0” to “7” a received-signal point viewed from the outputside of the remapper 7 corresponds. Because the signal arrangement ofthe portion of bit (0) (or bit (1)) of a frame-synchronizing signal atthe transmission side is determined as “0” (or “4”), areceived-signal-phase rotation angle viewed from the output side of theremapper 7 is univocally obtained from phase error data Δφ(3) and i′(1).

When the delay circuits 90 and 91 delay the phase error data Δφ(3)output from the selector 16C and the sign bit data i′(1) of I symbolstream data I′(8) fetched from an output of the remapper 7 and theframe-sync detecting/regenerating circuit 2 acquires aframe-synchronizing signal from I and Q symbol-stream data I′(8) andQ′(8) and starts outputting a regenerated frame-synchronizing signal,the received-signal-phase rotation angle detecting circuit 8C firstadjusts timings so that phase error data Δφ(3) corresponding to the headof a frame-synchronizing-signal portion of I symbol-stream data I(8) isoutput from the delay circuit 90 and sign bit data i′(1) correspondingto the head of a frame-synchronizing-signal portion of I symbol-streamdata I′(8) is output from the delay circuit 91. Outputs of the delaycircuits 91 and 90 are input as a high-order bit and a low-order bit ofone input side of an adder 93.

When a certain time elapses after start of reception, the frame-syncdetecting/regenerating circuit 2 acquires a frame-synchronizing signalof I and Q symbol-streams I′(8) and Q′(8) and outputs a regeneratedframe-synchronizing signal. Then, a selector 94 selects A(4)=(0101) atthe portion of bit (0) of the regenerated frame-synchronizing signal tooutput it and selects B(4)=(1101) at the portion of bit (1) to outputit. The adder 93 adds one input and the other input at each bit positionof a 20-bit regenerated frame-synchronizing signal to output high-orderthree bits. Then, the adder 93 outputs a received-signal-phase rotationangle signal R(3) obtained by dividing a received-signal-phase rotationangle Θ viewed from the output side of the remapper 7 into 0, π/4, 2π/4,3π/4, 4π/4, 5π/4, 6π/4, and 7π/4 as shown in FIG. 2A, relating them toR=0 to 7 of decimal notation, and expressing R by a three-bit naturalbinary number (refer to FIG. 2B).

The averaging circuit 95 captures outputs of the adder 93 whileinputting frame-synchronizing-signal-interval signals from theframe-sync detecting/regenerating circuit 2, averages the outputs forfour frames similarly to the case of FIG. 1, and outputs the averagingresult as a received-signal-phase rotation angle signal AR(3). The AR(3)is added with a holding value of the register 111 by the adder 110.However, because the holding value is (000) at first, the averagingcircuit 95 directly outputs the AR(3) to the remapper 7 as areceived-signal-phase rotation angle signal OR(3) against thetransmission side viewed from an output point of the demodulatingcircuit 1C and moreover, outputs the AR(3) to the register 111 to makethe register 111 hold the AR(3). For example, when areceived-signal-phase rotation angle Θ shown by the OR(3) is equal to3π/4, the remapper 7 phase-rotates by −3π/4 to generate an absolutephase. The register 111 holds (011).

(2) Normal Receiving Operation

Immediately after the frame-sync detecting/regenerating circuit 2acquires a frame-synchronizing signal, the transmission-configurationidentifying circuit 9 identifies a multiple configuration and outputs amodulation-system identifying signal DM showing to whichmodulation-system portion the present I and Q symbol streams I(8) andQ(8) output from the demodulating circuit 1C correspond, to the selector16C or the like.

When a received-signal-phase rotation angle signal OR(3) is output fromthe adder 110 and an absolute phase is generated by the remapper 7, theselector 16C enables only the phase error table 13 while thedemodulating circuit 1C demodulates the 8PSK-modulation-system portionand a symbol clock CLK_(SYB) is activated by using the modulation-systemidentifying signal DM input from the transmission-configurationidentifying circuit 9 and reads out of the phase error table 13 phaseerror data Δφ(8) corresponding to I and Q symbol-stream data I′(8) andQ′(8) to output the data Δφ(8) to the D/A converter 17. As a result, atthe time of considering phases of I′(8) and Q′(8) rotate by η=−Θ=−3π/4compared to the case of I(8) and Q(8), phases of the reference carrierwaves f_(c1) and f_(c2) are corrected so that received-signal points ofdigital signals (abc) 8PSK-mapped to transmission-side signal pointarrangements “0”, “1”, “2,” “3”, “4”, “5”, “6”, and “7” appear on signalpoint arrangements “3”, “4”, “5”, “6”, “7”, “0”, “1”, and “2”respectively phase-rotated by Θ viewed from the input side of theremapper 7.

In this case, phases of I and Q symbol-stream data I(8) and Q(8) at the8PSK-modulation-system portion output from the demodulating circuit 1Care rotated by the remapper 7 by η=−Θ=−3π/4 and absolute phases aregenerated. Therefore, received-signal points of I and Q symbol-streamdata I′(8) and Q′(8) output from the remapper 7 coincide with those ofthe transmission side.

The selector 16C enables only the phase error table 14-1 while thedemodulating circuit 1C demodulates the QPSK-modulation-system portionand the symbol clock CLK_(SYB) is activated and reads out of the phaseerror table 14-1 phase error data Δφ(8) corresponding to I and Qsymbol-stream data I′(8) and Q′(8) to output the data Δφ(8) to the D/Aconverter 17. Thereby, at the time of considering that phases of theI′(8) and Q′(8) rotate by η=−Θ=−3π/4 compared to the case of I(8) andQ(8), phases of the reference carrier waves f_(c1) and f_(c2) arecorrected so that digital signals (de) QPSK-mapped to transmission-sidesignal point arrangements “1”, “3”, “5”, and “7” appear on signal pointarrangements “4”, “6”, “0”, and “2” viewed from the input side of theremapper 7. Therefore, the digital signals (de) are held at the samerotation angle as the received-signal-phase rotation angle Θ at 8PSK.Because phases of the I and Q symbol-stream data I(8) and Q(8) at theQPSK-modulation-system portion output from the demodulating circuit 1Care rotated by the remapper 7 by −Θ=−3π/4, received-signal points of Iand Q symbol stream data I′(8) and Q′(8) output from the remapper 7coincide with those of the transmission side.

The selector 16C enables only the phase error table 15-1 while thedemodulating circuit 1C demodulates the BPSK-modulation-system portionand the symbol clock CLK_(SYB) is activated and reads out of the phaseerror table 15-1 phase error data Δφ(8) corresponding to I and Qsymbol-stream data I′(8) and Q′(8) to output the data Δφ(8) to the D/Aconverter 17. Thereby, at the time of considering that phases of theI′(8) and Q′(8) rotate by −Θ=−3π/4 compared to the case of I(8) andQ(8), phases of the reference carrier waves f_(c1) and f_(c2) arecorrected so that digital signals (f) BPSK-mapped to transmission-sidesignal point arrangements “0” and “4” appear on signal pointarrangements “3” and “7” viewed from the input side of the remapper 7.Therefore, the signals (f) are held at the same rotation angle as thereceived-signal-phase rotation angle Θ at 8PSK. Because phases of I andQ symbol-stream data I(8) and Q(8) at the BPSK-modulation-system portionoutput from the demodulating circuit 1C are rotated by the remapper 7 by−Θ=−3π/4, received-signal points of I and Q symbol-stream data I′(8) andQ′(8) coincide with those of the transmission side.

Also under the normal receiving operation, the selector 16C enables onlythe phase error table 15-1 while the symbol clock CLK_(SYB) is notactivated and reads from the phase error table 15-1 phase error dataΔφ(3) corresponding to I and Q symbol-stream data I(8)′ and Q(8)′ outputfrom the remapper 7 while the symbol clock CLK_(SYB) is not activated tooutput the data Δφ(3) to the delay circuit 90. Moreover, thephase-rotation-angle discriminating circuit 92 discriminates a phaserotation angle in accordance with an output of the delay circuit 90 or91 to output discrimination results in the form of received-signal-phaserotation angle signals R(3) and the averaging circuit 95 averages thesignals R(3) for four frames to output the averaging result as areceived-signal-phase rotation angle signal AR(3).

When the phase-rotation-angle discriminating circuit 92 and averagingcircuit 95 of the received-signal-phase rotation angle detecting circuit8C perform second-time phase-rotation-angle detection and output areceived-signal-phase rotation angle signal AR(3), thereceived-signal-phase rotation angle signal AR(3) shows a phase rotationangle against the transmission side viewed from I′(8) and Q′(8) aftertheir absolute phases are generated by the remapper 7. Therefore, byadding the signal AR(3) with the last-time received-signal-phaserotation angle signal OR(3) held by the register 111, areceived-signal-phase rotation angle signal OR(3) against thetransmission side viewed from the input side of the remapper 7 isobtained and the received-signal-phase rotation angle signal OR(3) isoutput to the remapper 7 to make the remapper 7 perform second-timephase rotation (at the time of assuming a received-signal-phase rotationangle shown by the OR(3) as Θ, the demapper 7 performs phase rotation by−Θ) and to make the register 110 hold the signal OR(3). Hereafter, thesame processing is repeated whenever the phase-rotation-anglediscriminating circuit 92 and averaging circuit 95 of thereceived-signal-phase rotation angle detecting circuit 8C detect a newphase rotation angle.

According to this embodiment, I and Q symbol-stream data I′(8) and Q′(8)after their absolute phases are generated by the remapper 7 are input tophase error tables of the carrier-wave regenerating circuit 10C.Therefore, received-signal points of I and Q symbol-stream data I′(8)and Q′(8) input to phase error tables become the same as those of thetransmission side independently of a value of a received-signal-phaserotation angle under normal reception. Therefore, it is enough toprovide one phase error table for the carrier-wave regenerating circuit10 every modulation system. Thus, it is possible to decrease the numberof phase error tables provided for the carrier-wave regenerating circuit10C and greatly simplify the circuit configuration.

Though the embodiment in FIG. 7 uses sign bit data i′(1) of Isymbol-stream data I′(8), it is also permitted to use sign bit dataserving as the MSB of Q symbol-stream data Q′(8).

The configuration in FIG. 7 can be modified to that in FIG. 8. That is,the carrier-wave regenerating circuit 10C of the demodulating circuit 1Din FIG. 8 is provided with three phase error tables 13, 14-1, and 15-1so as to read phase error data Δφ(3) corresponding to I and Qsymbol-stream data I′(8) and Q′(8) out of the phase error table 14-1while a symbol clock CLK_(SYB) is not activated. A received-signal-phaserotation angle detecting circuit 8D is configured by replacing portionsof the delay circuits 90 and 91 and phase-rotation-angle discriminatingcircuit 92 of the received-signal-phase rotation angle detecting circuit8C in FIG. 7 with the delay circuits 90, 91, and 99 and thephase-rotation-angle discriminating circuit 92B in FIG. 5. A selector16D inputs phase error data Δφ(3) read out of the phase error table 14-1to the delay circuit 90 while a symbol clock CLK_(SYB) is not activated.Moreover, the selector 16D is able to detect a phase rotation angleagainst the transmission side viewed from the output side of theremapper 7 by the delay circuits 90, 91, and 99, thephase-rotation-angle discriminating circuit 92B, and the averagingcircuit 95 in accordance with phase error data Δφ(3) read out of thephase error table 14-1 for QPSK and sign bit data i′(1) and q′(1) of Iand Q symbol-stream data I′(8) and Q′(8) similarly to the case of FIG. 5and output received-signal-rotation-angle signal OR(3) against thetransmission side viewed from the input side of the remapper 7 from theadder 110 by inputting the MSB of I symbol-stream data I′(8) output fromthe remapper 7 to the delay circuit 91 and the MSB of Q symbol-streamdata Q′(8) output from the remapper 7 to the delay circuit 99.

Moreover, the configuration in FIG. 7 can be modified to like that inFIG. 9. In FIG. 9, the received-signal-phase rotation angle detectingcircuit 8C is replaced with the received-signal-phase rotation angledetecting circuit 8A in FIG. 1. Furthermore, the demodulating circuit 1Cin FIG. 7 is modified to like a demodulating circuit 1E. A selector 19is provided for the input side of I and Q symbol-stream data I′(8) andQ′(8) of each of phase error tables 13, 14-1, and 15-1 so as to input Iand Q symbol-stream data I′(8) and Q′(8) to phase error tables 13, 14-1,and 15-1 output from remapper 7 while a symbol clock CLK_(SYB) isactivated and input I and Q symbol-stream data I(8) and Q(8) output fromthe demodulating circuit 1E to the phase error tables 13, 14-1, and 15-1while the symbol clock CLK_(SYB) is not activated.

Then, the selector 16C of the carrier-wave regenerating circuit 10Cenables only the phase error table 13 for 8PSK while the symbol clockCLK_(SYB) is activated before the transmission-configuration identifyingcircuit 9 identifies a multiple configuration of a frame and thereceived-signal-phase rotation angle detecting circuit 8A detects areceived-signal-phase rotation angle after start of reception and readsout of the phase error table 13 phase error data Δφ(8) corresponding toI and Q symbol-stream data I′(8) and Q′(8) input from the remapper 7through the selector 19 while the symbol clock CLK_(SYB) is activated tooutput the data Δφ(8) to the D/A converter 17.

Moreover, at the same time as the above, the selector 16C enables onlythe phase error table 15-1 while the symbol clock CLK_(SYB) is notactivated and reads out of the phase error table 15-1 phase error dataΔφ(3) of high-order three bits in the phase error data Δφ(8)corresponding to I and Q symbol-stream data I(8) and Q(8) input throughthe selector 19 while the symbol clock CLK_(SYB) is not activated tooutput the data Δφ(3) to the delay circuit 90.

Furthermore, after the transmission-configuration identifying circuit 9identifies a multiple configuration of a frame and thereceived-signal-phase rotation angle detecting circuit 8A detects areceived-signal-phase rotation angle Θ, the selector 16C enables onlyone phase error table corresponding to a modulation system of a receivedsignal demodulated by the demodulating circuit 1E among the phase errortables 13, 14-1, and 15-1 while the symbol clock CLK_(SYB) is activatedand reads phase error,data Δφ(8) corresponding to I and Q symbol-streamdata I′(8) and Q′(8) input from the remapper 7 through the selector 19while the symbol clock CLK_(SYB) is activated to output the data Δφ(8)to the D/A converter 17. Moreover, the selector 16C enables only thephase error table 15-1 for BPSK while the symbol clock CLK_(SYB) is notactivated so as to read out of the phase error table 15-1 phase errordata Δφ(3) of high-order three bits in the phase error data Δφ(8)corresponding to I and Q symbol-stream data I(8) and Q(8) input throughthe selector 19 while the symbol clock CLK_(SYB) is not activated. Thus,because a received-signal-phase rotation angle signal AR(3) against thetransmission side viewed from the input side of the remapper 7 can beoutput from the averaging circuit 95 similarly to the case of FIG. 1, itis possible to omit the adder 110 and register 111 in FIG. 7.

The configuration in FIG. 8 can be also modified to that in FIG. 10. InFIG. 10, the received-signal-phase rotation angle detecting circuit 8Din FIG. 8 is replaced with the received-signal-phase rotation angledetecting circuit 8B in FIG. 5. Moreover, the demodulating circuit 1D inFIG. 8 is modified to a demodulating circuit 1F. A selector 19 isprovided for the input side of I and Q symbol-stream data I′(8) andQ′(8) of each of phase error tables 13, 14-1, and 15-1 so as to input Iand Q symbol-stream data I′(8) and Q′(8) output from the remapper 7 tothe phase error tables 13, 14-1, and 15-1 while a symbol clock CLK_(SYB)is activated and input I and Q symbol-stream data I(8) and Q(8) outputfrom the demodulating circuit 1F to the phase error tables 13, 14-1, and15-1 while the symbol clock CLK_(SYB) is not activated.

Moreover, a selector 16D of a carrier-wave regenerating circuit 10Denables only the phase error table 13 for 8PSK while the symbol clockCLK_(SYB) is activated before the transmission-configuration identifyingcircuit 9 identifies a multiple configuration of a frame and thereceived-signal-phase rotation angle detecting circuit 8B detects areceived-signal-phase rotation angle after start of reception and readsout of the phase error table 13 phase error data Δφ(8) corresponding toI and Q symbol-stream data I′(8) and Q′(8) input from the remapper 7through the selector 19 while the symbol clock CLK_(SYB) is activated tooutput the data Δφ(8) to the D/A converter 17.

Moreover, at the same time as the above, the selector 16D enables onlythe phase error table 14-1 for QPSK while the symbol clock CLK_(SYB) isnot activated and reads out of the phase error table 14-1 phase errordata Δφ(3) of high-order three bits in the phase error data Δφ(8)corresponding to I and Q symbol-stream data I(8) and Q(8) input throughthe selector 19 while the symbol clock CLK_(SYB) is not activated tooutput the data Δφ(3) to the delay circuit 90.

After the transmission-configuration identifying circuit 9 identifies amultiple configuration of a frame and the received-signal-phase rotationangle detecting circuit 8B detects a received-signal-phase rotationangle Θ, the selector 16D enables only one phase error tablecorresponding to a modulation system of a received signal demodulated bythe demodulating circuit 1F among the phase error tables 13, 14-1 and15-1 while the symbol clock CLK_(SYB) is activated and reads phase errordata Δφ(8) corresponding to I and Q symbol-stream data I′(8) and Q′(8)input from the remapper 7 through the selector 19 while the symbol clockCLK_(SYB) is activated to output the data Δφ(8) to the D/A converter 17.Moreover, the selector 16D enables only the phase error table 14-1 forQPSK while the symbol clock CLK_(SYB) is not activated so as to read outof the phase error table 14-1 phase error data Δφ(3) of high-order threebits in the phase error data Δφ(8) corresponding to I and Qsymbol-stream data I(8) and Q(8) input through the selector 19 while thesymbol clock CLK_(SYB) is not activated . Thus, because areceived-signal-phase rotation angle signal AR(3) against thetransmission side viewed from the input side of the remapper 7 can beoutput from the averaging circuit 95 similarly to the case of FIG. 5, itis possible to omit the adder 110 and register 111 in FIG. 8.

In case of the above embodiments and their modifications, a multipleconfiguration is identified by a transmission-configuration identifyingcircuit after start of reception and a selector of a carrier-waveregenerating circuit outputs phase error data read out of a phase errortable for 8PSK to a D/A converter before a received-signal-phaserotation angle is detected by a received-signal-phase rotation angledetecting circuit. However, it is also permitted to output a constantvalue showing phase error=zero instead.

Moreover, in the case of the above embodiments and their modifications,not only a BPSK-modulated frame-synchronizing signal but also aPSK-modulated signal (PSK-modulated wave) in which digital signalsaccording to three modulation systems of 8PSK, QPSK, and BPSK aretime-multiplexed are used. However, it is also possible to apply theembodiments and their modifications to a case of receiving anddemodulating a signal to be PSK-modulated in which only a BPSK-modulatedframe-synchronizing signal and 8PSK-modulated digital signal aretime-multiplexed (it is enough to prepare a phase error table for 8PSKand a phase error table for BPSK) or a case of receiving anddemodulating a signal to be PSK-modulated in which a BPSK-modulatedframe-synchronizing signal, an 8PSK-modulated digital signal, and aQPSK-modulated digital signal are time-multiplexed.

Moreover, the embodiments and their modifications can be applied to acase in which a demodulating circuit performs a demodulating operationthrough semi-synchronous detection instead of performing a demodulatingoperation through synchronous detection.

INDUSTRIAL APPLICABILITY

According to the present invention, a received-signal-phase rotationangle is univocally determined by a high-order bit of phase error dataaccording to a phase error table for BPSK (QPSK) modulationcorresponding to demodulated I and Q symbol-stream data and sign bitdata of I or Q (I and Q) symbol-stream data at a portion correspondingto bit (0) (or bit (1)) of a frame-synchronizing signal and it can bediscriminated through a simple operation. Therefore, it is unnecessaryto use a large ROM dedicated to discrimination of a phase rotation angleand it is possible to decrease a circuit size.

What is claimed is:
 1. An apparatus for generating an absolute phase ofa signal received by a receiver, said receiver comprising demodulatingmeans for demodulating a signal to be PSK-modulated in which at least an8PSK-modulated digital signal among an 8PSK-modulated digital signal, aQPSK-modulated digital signal, and a BPSK-modulated digital signal istime-multiplexed with a BPSK-modulated frame-synchronizing signal, byusing carrier waves (f_(c1) and f_(c2)) regenerated by carrier-waveregenerating means and outputting I and Q symbol-stream data (I(8) andQ(8)); frame-synchronizing-signal acquiring means (2) for acquiring aframe-synchronizing signal from the demodulated I and Q symbol-streamdata; received-signal-phase rotation angle detecting means for detectinga phase rotation angle (R(3)) of I and Q symbol-stream data output fromthe demodulating means against the transmission side; and antiphaserotating means (7) for antiphase-rotating a phase of I and Qsymbol-stream data output from the demodulating means by a phaserotation angle (R(3)) detected by the received-signal-phase rotationangle detecting means so that the carrier-wave regenerating means of thedemodulating means has phase error tables (13, 14-1, and 15-1 to 15-4)storing carrier-wave phase error data (Δφ(8)) for various demodulated Iand Q symbol-stream data sets for each modulation system, reads phaseerror data corresponding to the demodulated I and Q symbol-stream datafrom a phase error table of a corresponding modulation system while thedemodulating means demodulates a certain modulation-system portion uponnormal reception, and corrects a phase of a carrier wave; wherein saidapparatus is characterized in that said received-signalphase-rotation-angle detecting means (8A, 8B, 8C, or 8D) includephase-error-data reading means (16A, 16B, 16C, and 16D) for readinghigh-order bits (Δφ(3) and (Δφ′(3)) for judging whether the absolutevalue of a phase error is larger or smaller than (π/8)+s·(π/4) (s is 0or 1) or π/8 among phase error data corresponding to the demodulated Iand Q symbol-stream data from a phase error table (15-1 to 15-4 or 14-1,14-2) for BPSK modulation of the carrier-wave regenerating means (10A,10B, 10C or 10D) and discriminating means (92 or 92B) for discriminatinga phase rotation angle of a symbol portion corresponding to bit (0) (orbit (1)) of a frame-synchronizing signal against the transmission sidein I and Q symbol-stream data output from demodulating means (1A, 1B,1C, 1D, 1E, or 1F) in accordance with the sign bit data (i(1) and i′(1))of I (or Q) symbol-stream data of a portion corresponding to bit (0) (orbit (1)) of a frame-synchronizing signal acquired by theframe-synchronizing-signal acquiring means in demodulated I and Qsymbol-stream data (I(8) or Q(8)) and phase error data (Δφ(8) or(Δφ′(8)) read by the phase error data reading means correspondingly tothe portion and outputting a discrimination result (R(3)).
 2. A receiverfor receiving a signal to be PSK-modulated obtained by time-multiplexinga BPSK-modulated frame-synchronizing signal and a digital signalmodulated by a predetermined modulation system, from a transmitter, saidreceiver comprising: demodulating means for demodulating the signal tobe PSK-modulated and generating I and Q symbol-stream data (I(8) andQ(8)); frame-synchronizing-signal acquiring means (2) for acquiring aframe-synchronizing signal from the I and Q symbol-stream data;received-signal-phase rotation angle detecting means for detecting aphase difference between I and Q symbol-stream data to the transmitterside; and antiphase rotating means (7) for inversely-rotating a phase ofI and Q symbol-stream data by a phase difference (R(3)) detected by thereceived-signal-phase rotation angle detecting means to generate I and Qsymbol-stream data (I′(8) and Q′(8)) in which a transmitter-side phaseangle coincides with a receiver-side phase angle so that saiddemodulating means includes carrier-wave regenerating means forregenerating a carrier wave used to perform demodulation, and saidcarrier-wave regenerating means has phase error tables (13, 14-1, and15-1 to 15-4) for storing carrier-wave phase error data (φ(8))corresponding to I and Q symbol-stream data generated by thedemodulating means and generates a carrier wave synchronizing with acarrier wave used for the transmitter side in accordance with thecarrier-wave phase error data (Δφ(8)), wherein saidreceived-signal-phase rotation angle detecting means (8A, 8B, 8C, or 8D)detect the phase difference in accordance with at least either of parts(Δφ(3) or Δφ′(3)) of the carrier-wave phase error data (Δφ(8) or Δφ′(8))and I and Q symbol-stream data and a frame-synchronizing signal acquiredby the frame-synchronizing-signal acquiring means and supply the phasedifference to the antiphase rotating means.